Commit a08903f0 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
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clk: renesas: rzg2l: Update error message 



Update the error message in `rzg2l_mod_clock_endisable()` to provide
clearer debugging information. Instead of printing only the register
address, include both the `CLK_ON_R(reg)` offset and the corresponding
`clk` name (`%pC`). This enhances readability and aids in debugging
clock enable failures.

Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250211105603.195905-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 5a1cb35b

drivers/clk/renesas/rzg2l-cpg.c

+2 −2
Original line number Diff line number Diff line
@@ -1239,8 +1239,8 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) 
	error = readl_poll_timeout_atomic(priv->base + CLK_MON_R(reg), value,

					  value & bitmask, 0, 10);

	if (error)

		dev_err(dev, "Failed to enable CLK_ON %p\n",

			priv->base + CLK_ON_R(reg));

		dev_err(dev, "Failed to enable CLK_ON 0x%x/%pC\n",

			CLK_ON_R(reg), hw->clk);



	return error;

}