Commit a09b2d6a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.10-tag1' of... 

Merge tag 'renesas-clk-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add thermal, serial (SCIF), and timer (CMT/TMU) clocks on R-Car V4M
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779h0: Add timer clocks
  clk: renesas: r8a779h0: Add SCIF clocks
  clk: renesas: r9a07g044: Mark resets array as const
  clk: renesas: r9a07g043: Mark mod_clks and resets arrays as const
  clk: renesas: r8a779h0: Add thermal clock
  dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks
parents 4cece764 c0516eb4

drivers/clk/renesas/r8a779h0-cpg-mssr.c

+14 −0
Original line number Diff line number Diff line
@@ -185,13 +185,27 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = { 
	DEF_MOD("i2c2",		520,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("i2c3",		521,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("rpc-if",	629,	R8A779H0_CLK_RPCD2),

	DEF_MOD("scif0",	702,	R8A779H0_CLK_SASYNCPERD4),

	DEF_MOD("scif1",	703,	R8A779H0_CLK_SASYNCPERD4),

	DEF_MOD("scif3",	704,	R8A779H0_CLK_SASYNCPERD4),

	DEF_MOD("scif4",	705,	R8A779H0_CLK_SASYNCPERD4),

	DEF_MOD("sdhi0",	706,	R8A779H0_CLK_SD0),

	DEF_MOD("sydm1",	709,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("sydm2",	710,	R8A779H0_CLK_S0D6_PER),

	DEF_MOD("tmu0",		713,	R8A779H0_CLK_SASYNCRT),

	DEF_MOD("tmu1",		714,	R8A779H0_CLK_SASYNCPERD2),

	DEF_MOD("tmu2",		715,	R8A779H0_CLK_SASYNCPERD2),

	DEF_MOD("tmu3",		716,	R8A779H0_CLK_SASYNCPERD2),

	DEF_MOD("tmu4",		717,	R8A779H0_CLK_SASYNCPERD2),

	DEF_MOD("wdt1:wdt0",	907,	R8A779H0_CLK_R),

	DEF_MOD("cmt0",		910,	R8A779H0_CLK_R),

	DEF_MOD("cmt1",		911,	R8A779H0_CLK_R),

	DEF_MOD("cmt2",		912,	R8A779H0_CLK_R),

	DEF_MOD("cmt3",		913,	R8A779H0_CLK_R),

	DEF_MOD("pfc0",		915,	R8A779H0_CLK_CP),

	DEF_MOD("pfc1",		916,	R8A779H0_CLK_CP),

	DEF_MOD("pfc2",		917,	R8A779H0_CLK_CP),

	DEF_MOD("tsc2:tsc1",	919,	R8A779H0_CLK_CL16M),

};



/*

drivers/clk/renesas/r9a07g043-cpg.c

+2 −2
Original line number Diff line number Diff line
@@ -149,7 +149,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 
#endif

};



static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {

static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = {

#ifdef CONFIG_ARM64

	DEF_MOD("gic",		R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,

				0x514, 0),
@@ -282,7 +282,7 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 
				0x5ac, 0),

};



static struct rzg2l_reset r9a07g043_resets[] = {

static const struct rzg2l_reset r9a07g043_resets[] = {

#ifdef CONFIG_ARM64

	DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),

	DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),

drivers/clk/renesas/r9a07g044-cpg.c

+1 −1
Original line number Diff line number Diff line
@@ -368,7 +368,7 @@ static const struct { 
#endif

};



static struct rzg2l_reset r9a07g044_resets[] = {

static const struct rzg2l_reset r9a07g044_resets[] = {

	DEF_RST(R9A07G044_GIC600_GICRESET_N, 0x814, 0),

	DEF_RST(R9A07G044_GIC600_DBG_GICRESET_N, 0x814, 1),

	DEF_RST(R9A07G044_IA55_RESETN, 0x818, 0),

include/dt-bindings/clock/r9a07g043-cpg.h

+3 −3
Original line number Diff line number Diff line
@@ -16,15 +16,15 @@ 
#define R9A07G043_CLK_SD0		5

#define R9A07G043_CLK_SD1		6

#define R9A07G043_CLK_M0		7

#define R9A07G043_CLK_M2		8

#define R9A07G043_CLK_M3		9

#define R9A07G043_CLK_M2		8	/* RZ/G2UL Only */

#define R9A07G043_CLK_M3		9	/* RZ/G2UL Only */

#define R9A07G043_CLK_HP		10

#define R9A07G043_CLK_TSU		11

#define R9A07G043_CLK_ZT		12

#define R9A07G043_CLK_P0		13

#define R9A07G043_CLK_P1		14

#define R9A07G043_CLK_P2		15

#define R9A07G043_CLK_AT		16

#define R9A07G043_CLK_AT		16	/* RZ/G2UL Only */

#define R9A07G043_OSCCLK		17

#define R9A07G043_CLK_P0_DIV2		18