Commit a1c3a7d7 authored by Junhui Liu's avatar Junhui Liu Committed by Thomas Gleixner
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dt-bindings: interrupt-controller: Add Anlogic DR1V90 ACLINT SSWI 



Add SSWI support for Anlogic DR1V90 SoC, which uses Nuclei UX900 with a
TIMER unit compliant with the ACLINT specification.

Signed-off-by: default avatarJunhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251021-dr1v90-basic-dt-v3-6-5478db4f664a@pigmoral.tech
parent 579951da

Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-sswi.yaml

+4 −0
Original line number Diff line number Diff line
@@ -30,6 +30,10 @@ properties: 
          - const: thead,c900-aclint-sswi

      - items:

          - const: mips,p8700-aclint-sswi

      - items:

          - enum:

              - anlogic,dr1v90-aclint-sswi

          - const: nuclei,ux900-aclint-sswi



  reg:

    maxItems: 1