Commit ad7108f9 authored by Suraj Kandpal's avatar Suraj Kandpal
Browse files

drm/i915/ltphy: Modify the step that need to be skipped 



Bspec has changed the non tbt pll enable sequence now we skip
steps 5-17 if no config change has occurred.

Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: default avatarArun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-26-suraj.kandpal@intel.com
parent e34c6356

drivers/gpu/drm/i915/display/intel_lt_phy.c

+33 −30
Original line number Diff line number Diff line
@@ -1677,11 +1677,11 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, 
					 XE3PLPD_MACCLK_TURNON_LATENCY_US, 2, NULL))

			drm_warn(display->drm, "PHY %c PLL MacCLK Ack assertion Timeout after %dus.\n",

				 phy_name(phy), XE3PLPD_MACCLK_TURNON_LATENCY_US);

	} else {

		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);

	}



	/* 13. Ungate the forward clock by setting PORT_CLOCK_CTL[Forward Clock Ungate] = 1. */

		/*

		 * 13. Ungate the forward clock by setting

		 * PORT_CLOCK_CTL[Forward Clock Ungate] = 1.

		 */

		intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),

			     XELPDP_FORWARD_CLOCK_UNGATE,

			     XELPDP_FORWARD_CLOCK_UNGATE);
@@ -1691,8 +1691,8 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, 
			     lane_phy_pulse_status,

			     lane_phy_pulse_status);

		/*

	 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over PHY message bus for

	 * Owned PHY Lanes.

		 * 15. Clear the PHY VDR register 0xCC4[Rate Control VDR Update] over

		 * PHY message bus for Owned PHY Lanes.

		 */

		rate_update = intel_lt_phy_read(encoder, INTEL_LT_PHY_LANE0, LT_PHY_RATE_UPDATE);

		rate_update &= ~LT_PHY_RATE_CONTROL_VDR_UPDATE;
@@ -1710,6 +1710,9 @@ void intel_lt_phy_pll_enable(struct intel_encoder *encoder, 
		intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),

			     lane_phy_pulse_status,

			     lane_phy_pulse_status);

	} else {

		intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), crtc_state->port_clock);

	}



	/*

	 * 18. Follow the Display Voltage Frequency Switching - Sequence After Frequency Change.