Merge branches 'arm/smmu', 'mediatek', 's390', 'ti/omap', 'riscv' and 'core' into next (ae3325f7) · Commits · git / linux-nf

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

+5 −0

Original line number	Diff line number	Diff line
		@@ -36,10 +36,12 @@ properties:
		items:
		- enum:
		- qcom,qcm2290-smmu-500
		- qcom,qcs615-smmu-500
		- qcom,qcs8300-smmu-500
		- qcom,qdu1000-smmu-500
		- qcom,sa8255p-smmu-500
		- qcom,sa8775p-smmu-500
		- qcom,sar2130p-smmu-500
		- qcom,sc7180-smmu-500
		- qcom,sc7280-smmu-500
		- qcom,sc8180x-smmu-500
		@@ -88,6 +90,7 @@ properties:
		- qcom,qcm2290-smmu-500
		- qcom,sa8255p-smmu-500
		- qcom,sa8775p-smmu-500
		- qcom,sar2130p-smmu-500
		- qcom,sc7280-smmu-500
		- qcom,sc8180x-smmu-500
		- qcom,sc8280xp-smmu-500
		@@ -524,6 +527,7 @@ allOf:
		compatible:
		items:
		- enum:
		- qcom,sar2130p-smmu-500
		- qcom,sm8550-smmu-500
		- qcom,sm8650-smmu-500
		- qcom,x1e80100-smmu-500
		@@ -555,6 +559,7 @@ allOf:
		- cavium,smmu-v2
		- marvell,ap806-smmu-500
		- nvidia,smmu-500
		- qcom,qcs615-smmu-500
		- qcom,qcs8300-smmu-500
		- qcom,qdu1000-smmu-500
		- qcom,sa8255p-smmu-500

Documentation/devicetree/bindings/iommu/riscv,iommu.yaml

0 → 100644

+147 −0

Original line number	Diff line number	Diff line
		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: RISC-V IOMMU Architecture Implementation

		maintainers:
		- Tomasz Jeznach <tjeznach@rivosinc.com>

		description: \|
		The RISC-V IOMMU provides memory address translation and isolation for
		input and output devices, supporting per-device translation context,
		shared process address spaces including the ATS and PRI components of
		the PCIe specification, two stage address translation and MSI remapping.
		It supports identical translation table format to the RISC-V address
		translation tables with page level access and protection attributes.
		Hardware uses in-memory command and fault reporting queues with wired
		interrupt or MSI notifications.

		Visit https://github.com/riscv-non-isa/riscv-iommu for more details.

		For information on assigning RISC-V IOMMU to its peripheral devices,
		see generic IOMMU bindings.

		properties:
		# For PCIe IOMMU hardware compatible property should contain the vendor
		# and device ID according to the PCI Bus Binding specification.
		# Since PCI provides built-in identification methods, compatible is not
		# actually required. For non-PCIe hardware implementations 'riscv,iommu'
		# should be specified along with 'reg' property providing MMIO location.
		compatible:
		oneOf:
		- items:
		- enum:
		- qemu,riscv-iommu
		- const: riscv,iommu
		- items:
		- enum:
		- pci1efd,edf1
		- const: riscv,pci-iommu

		reg:
		maxItems: 1
		description:
		For non-PCI devices this represents base address and size of for the
		IOMMU memory mapped registers interface.
		For PCI IOMMU hardware implementation this should represent an address
		of the IOMMU, as defined in the PCI Bus Binding reference.

		'#iommu-cells':
		const: 1
		description:
		The single cell describes the requester id emitted by a master to the
		IOMMU.

		interrupts:
		minItems: 1
		maxItems: 4
		description:
		Wired interrupt vectors available for RISC-V IOMMU to notify the
		RISC-V HARTS. The cause to interrupt vector is software defined
		using IVEC IOMMU register.

		msi-parent: true

		power-domains:
		maxItems: 1

		required:
		- compatible
		- reg
		- '#iommu-cells'

		additionalProperties: false

		examples:
		- \|+
		/* Example 1 (IOMMU device with wired interrupts) */
		#include <dt-bindings/interrupt-controller/irq.h>

		iommu1: iommu@1bccd000 {
		compatible = "qemu,riscv-iommu", "riscv,iommu";
		reg = <0x1bccd000 0x1000>;
		interrupt-parent = <&aplic_smode>;
		interrupts = <32 IRQ_TYPE_LEVEL_HIGH>,
		<33 IRQ_TYPE_LEVEL_HIGH>,
		<34 IRQ_TYPE_LEVEL_HIGH>,
		<35 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		};

		/* Device with two IOMMU device IDs, 0 and 7 */
		master1 {
		iommus = <&iommu1 0>, <&iommu1 7>;
		};

		- \|+
		/* Example 2 (IOMMU device with shared wired interrupt) */
		#include <dt-bindings/interrupt-controller/irq.h>

		iommu2: iommu@1bccd000 {
		compatible = "qemu,riscv-iommu", "riscv,iommu";
		reg = <0x1bccd000 0x1000>;
		interrupt-parent = <&aplic_smode>;
		interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
		#iommu-cells = <1>;
		};

		- \|+
		/* Example 3 (IOMMU device with MSIs) */
		iommu3: iommu@1bcdd000 {
		compatible = "qemu,riscv-iommu", "riscv,iommu";
		reg = <0x1bccd000 0x1000>;
		msi-parent = <&imsics_smode>;
		#iommu-cells = <1>;
		};

		- \|+
		/* Example 4 (IOMMU PCIe device with MSIs) */
		bus {
		#address-cells = <2>;
		#size-cells = <2>;

		pcie@30000000 {
		device_type = "pci";
		#address-cells = <3>;
		#size-cells = <2>;
		reg = <0x0 0x30000000 0x0 0x1000000>;
		ranges = <0x02000000 0x0 0x41000000 0x0 0x41000000 0x0 0x0f000000>;

		/*
		* The IOMMU manages all functions in this PCI domain except
		* itself. Omit BDF 00:01.0.
		*/
		iommu-map = <0x0 &iommu0 0x0 0x8>,
		<0x9 &iommu0 0x9 0xfff7>;

		/* The IOMMU programming interface uses slot 00:01.0 */
		iommu0: iommu@1,0 {
		compatible = "pci1efd,edf1", "riscv,pci-iommu";
		reg = <0x800 0 0 0 0>;
		#iommu-cells = <1>;
		};
		};
		};

MAINTAINERS

+9 −0

Original line number	Diff line number	Diff line
		@@ -19810,6 +19810,15 @@ F: arch/riscv/
		N: riscv
		K: riscv

		RISC-V IOMMU
		M: Tomasz Jeznach <tjeznach@rivosinc.com>
		L: iommu@lists.linux.dev
		L: linux-riscv@lists.infradead.org
		S: Maintained
		T: git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git
		F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
		F: drivers/iommu/riscv/

		RISC-V MICROCHIP FPGA SUPPORT
		M: Conor Dooley <conor.dooley@microchip.com>
		M: Daire McNamara <daire.mcnamara@microchip.com>

arch/s390/include/asm/pci.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -96,7 +96,6 @@ struct zpci_bar_struct {
		u8 size; /* order 2 exponent */
		};

		struct s390_domain;
		struct kvm_zdev;

		#define ZPCI_FUNCTIONS_PER_BUS 256
		@@ -181,9 +180,10 @@ struct zpci_dev {
		struct dentry *debugfs_dev;

		/* IOMMU and passthrough */
		struct s390_domain s390_domain; / s390 IOMMU domain data */
		struct iommu_domain s390_domain; / attached IOMMU domain */
		struct kvm_zdev *kzdev;
		struct mutex kzdev_lock;
		spinlock_t dom_lock; /* protect s390_domain change */
		};

		static inline bool zdev_enabled(struct zpci_dev *zdev)

arch/s390/pci/pci.c

+3 −0

Original line number	Diff line number	Diff line
		@@ -160,6 +160,7 @@ int zpci_fmb_enable_device(struct zpci_dev *zdev)
		u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_SET_MEASURE);
		struct zpci_iommu_ctrs *ctrs;
		struct zpci_fib fib = {0};
		unsigned long flags;
		u8 cc, status;

		if (zdev->fmb \|\| sizeof(*zdev->fmb) < zdev->fmb_length)
		@@ -171,6 +172,7 @@ int zpci_fmb_enable_device(struct zpci_dev *zdev)
		WARN_ON((u64) zdev->fmb & 0xf);

		/* reset software counters */
		spin_lock_irqsave(&zdev->dom_lock, flags);
		ctrs = zpci_get_iommu_ctrs(zdev);
		if (ctrs) {
		atomic64_set(&ctrs->mapped_pages, 0);
		@@ -179,6 +181,7 @@ int zpci_fmb_enable_device(struct zpci_dev *zdev)
		atomic64_set(&ctrs->sync_map_rpcits, 0);
		atomic64_set(&ctrs->sync_rpcits, 0);
		}
		spin_unlock_irqrestore(&zdev->dom_lock, flags);


		fib.fmb_addr = virt_to_phys(zdev->fmb);