Commit ae7f6d59 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'mediatek-drm-next-6.14' of... 

Merge tag 'mediatek-drm-next-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux

 into drm-next

Mediatek DRM Next for Linux 6.14

1. dp: Add sdp path reset
2. dp: Support flexible length of DP calibration data

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20250104125538.111118-1-chunkuang.hu@kernel.org
parents 9cc06dba ba581156

drivers/gpu/drm/mediatek/mtk_dp.c

+28 −5
Original line number Diff line number Diff line
@@ -1135,6 +1135,18 @@ static void mtk_dp_digital_sw_reset(struct mtk_dp *mtk_dp) 
			   0, DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0);

}



static void mtk_dp_sdp_path_reset(struct mtk_dp *mtk_dp)

{

	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,

			   SDP_RESET_SW_DP_ENC0_P0,

			   SDP_RESET_SW_DP_ENC0_P0);



	/* Wait for sdp path reset to complete */

	usleep_range(1000, 5000);

	mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,

			   0, SDP_RESET_SW_DP_ENC0_P0);

}



static void mtk_dp_set_lanes(struct mtk_dp *mtk_dp, int lanes)

{

	mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35F0,
@@ -1165,17 +1177,25 @@ static void mtk_dp_get_calibration_data(struct mtk_dp *mtk_dp) 
	buf = (u32 *)nvmem_cell_read(cell, &len);

	nvmem_cell_put(cell);



	if (IS_ERR(buf) || ((len / sizeof(u32)) != 4)) {

	if (IS_ERR(buf)) {

		dev_warn(dev, "Failed to read nvmem_cell_read\n");



		if (!IS_ERR(buf))

			kfree(buf);



		goto use_default_val;

	}



	/* The cell length is in bytes. Convert it to be compatible with u32 buffer. */

	len /= sizeof(u32);



	for (i = 0; i < MTK_DP_CAL_MAX; i++) {

		fmt = &mtk_dp->data->efuse_fmt[i];



		if (fmt->idx >= len) {

			dev_warn(mtk_dp->dev,

				 "Out-of-bound efuse data access, fmt idx = %d, buf len = %zu\n",

				 fmt->idx, len);

			kfree(buf);

			goto use_default_val;

		}



		cal_data[i] = (buf[fmt->idx] >> fmt->shift) & fmt->mask;



		if (cal_data[i] < fmt->min_val || cal_data[i] > fmt->max_val) {
@@ -2397,6 +2417,9 @@ static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge, 
			   DP_PWR_STATE_BANDGAP_TPLL,

			   DP_PWR_STATE_MASK);



	/* SDP path reset sw*/

	mtk_dp_sdp_path_reset(mtk_dp);



	/* Ensure the sink is muted */

	msleep(20);

}

drivers/gpu/drm/mediatek/mtk_dp_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ 
#define MTK_DP_ENC0_P0_3004			0x3004

#define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK		BIT(8)

#define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0		BIT(9)

#define SDP_RESET_SW_DP_ENC0_P0				BIT(13)

#define MTK_DP_ENC0_P0_3010			0x3010

#define HTOTAL_SW_DP_ENC0_P0_MASK			GENMASK(15, 0)

#define MTK_DP_ENC0_P0_3014			0x3014