Commit aec8c0e2 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Bjorn Andersson
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clk: qcom: rcg2: add clk_rcg2_shared_floor_ops 



Generally SDCC clocks use clk_rcg2_floor_ops, however on SAR2130P
platform it's recommended to use rcg2_shared_ops for all Root Clock
Generators to park them instead of disabling. Implement a mix of those,
clk_rcg2_shared_floor_ops.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-6-ecad2a1432ba@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent f93cea43

drivers/clk/qcom/clk-rcg.h

+1 −0
Original line number Diff line number Diff line
@@ -198,6 +198,7 @@ extern const struct clk_ops clk_byte2_ops; 
extern const struct clk_ops clk_pixel_ops;

extern const struct clk_ops clk_gfx3d_ops;

extern const struct clk_ops clk_rcg2_shared_ops;

extern const struct clk_ops clk_rcg2_shared_floor_ops;

extern const struct clk_ops clk_rcg2_shared_no_init_park_ops;

extern const struct clk_ops clk_dp_ops;

drivers/clk/qcom/clk-rcg2.c

+43 −5
Original line number Diff line number Diff line
@@ -1186,15 +1186,23 @@ clk_rcg2_shared_force_enable_clear(struct clk_hw *hw, const struct freq_tbl *f) 
	return clk_rcg2_clear_force_enable(hw);

}



static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,

				    unsigned long parent_rate)

static int __clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,

				      unsigned long parent_rate,

				      enum freq_policy policy)

{

	struct clk_rcg2 *rcg = to_clk_rcg2(hw);

	const struct freq_tbl *f;



	switch (policy) {

	case FLOOR:

		f = qcom_find_freq_floor(rcg->freq_tbl, rate);

		break;

	case CEIL:

		f = qcom_find_freq(rcg->freq_tbl, rate);

	if (!f)

		break;

	default:

		return -EINVAL;

	}



	/*

	 * In case clock is disabled, update the M, N and D registers, cache
@@ -1207,10 +1215,28 @@ static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate, 
	return clk_rcg2_shared_force_enable_clear(hw, f);

}



static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,

				    unsigned long parent_rate)

{

	return __clk_rcg2_shared_set_rate(hw, rate, parent_rate, CEIL);

}



static int clk_rcg2_shared_set_rate_and_parent(struct clk_hw *hw,

		unsigned long rate, unsigned long parent_rate, u8 index)

{

	return clk_rcg2_shared_set_rate(hw, rate, parent_rate);

	return __clk_rcg2_shared_set_rate(hw, rate, parent_rate, CEIL);

}



static int clk_rcg2_shared_set_floor_rate(struct clk_hw *hw, unsigned long rate,

					  unsigned long parent_rate)

{

	return __clk_rcg2_shared_set_rate(hw, rate, parent_rate, FLOOR);

}



static int clk_rcg2_shared_set_floor_rate_and_parent(struct clk_hw *hw,

		unsigned long rate, unsigned long parent_rate, u8 index)

{

	return __clk_rcg2_shared_set_rate(hw, rate, parent_rate, FLOOR);

}



static int clk_rcg2_shared_enable(struct clk_hw *hw)
@@ -1348,6 +1374,18 @@ const struct clk_ops clk_rcg2_shared_ops = { 
};

EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);



const struct clk_ops clk_rcg2_shared_floor_ops = {

	.enable = clk_rcg2_shared_enable,

	.disable = clk_rcg2_shared_disable,

	.get_parent = clk_rcg2_shared_get_parent,

	.set_parent = clk_rcg2_shared_set_parent,

	.recalc_rate = clk_rcg2_shared_recalc_rate,

	.determine_rate = clk_rcg2_determine_floor_rate,

	.set_rate = clk_rcg2_shared_set_floor_rate,

	.set_rate_and_parent = clk_rcg2_shared_set_floor_rate_and_parent,

};

EXPORT_SYMBOL_GPL(clk_rcg2_shared_floor_ops);



static int clk_rcg2_shared_no_init_park(struct clk_hw *hw)

{

	struct clk_rcg2 *rcg = to_clk_rcg2(hw);