Commit f93cea43 authored by Bjorn Andersson's avatar Bjorn Andersson
Browse files

Merge branch '20241027-sar2130p-clocks-v5-0-ecad2a1432ba@linaro.org' into clk-for-6.13 

Merge SAR2130P clock bindings through topic branch, to allow them being
used in both clock and DeviceTree branches.
parents 04bad0c9 11148102

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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@@ -19,6 +19,7 @@ properties: 
    enum:

      - qcom,qdu1000-rpmh-clk

      - qcom,sa8775p-rpmh-clk

      - qcom,sar2130p-rpmh-clk

      - qcom,sc7180-rpmh-clk

      - qcom,sc7280-rpmh-clk

      - qcom,sc8180x-rpmh-clk

Documentation/devicetree/bindings/clock/qcom,sar2130p-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sar2130p-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on sar2130p



maintainers:

  - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>



description: |

  Qualcomm global clock control module provides the clocks, resets and

  power domains on sar2130p.



  See also: include/dt-bindings/clock/qcom,sar2130p-gcc.h



properties:

  compatible:

    const: qcom,sar2130p-gcc



  clocks:

    items:

      - description: XO reference clock

      - description: Sleep clock

      - description: PCIe 0 pipe clock

      - description: PCIe 1 pipe clock

      - description: Primary USB3 PHY wrapper pipe clock



  protected-clocks:

    maxItems: 240



  power-domains:

    maxItems: 1



required:

  - compatible

  - clocks

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>



    gcc: clock-controller@100000 {

        compatible = "qcom,sar2130p-gcc";

        reg = <0x100000 0x1f4200>;

        clocks = <&rpmhcc RPMH_CXO_CLK>,

                 <&sleep_clk>,

                 <&pcie_0_pipe_clk>,

                 <&pcie_1_pipe_clk>,

                 <&usb_0_ssphy>;

        power-domains = <&rpmhpd RPMHPD_CX>;



        #clock-cells = <1>;

        #reset-cells = <1>;

        #power-domain-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml

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@@ -14,6 +14,7 @@ description: | 
  domains on Qualcomm SoCs.



  See also::

    include/dt-bindings/clock/qcom,sar2130p-gpucc.h

    include/dt-bindings/clock/qcom,sm4450-gpucc.h

    include/dt-bindings/clock/qcom,sm8450-gpucc.h

    include/dt-bindings/clock/qcom,sm8550-gpucc.h
@@ -24,6 +25,7 @@ description: | 
properties:

  compatible:

    enum:

      - qcom,sar2130p-gpucc

      - qcom,sm4450-gpucc

      - qcom,sm8450-gpucc

      - qcom,sm8475-gpucc

Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml

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@@ -22,6 +22,7 @@ description: | 
properties:

  compatible:

    enum:

      - qcom,sar2130p-dispcc

      - qcom,sm8550-dispcc

      - qcom,sm8650-dispcc

      - qcom,x1e80100-dispcc

Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml

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@@ -21,6 +21,7 @@ properties: 
  compatible:

    items:

      - enum:

          - qcom,sar2130p-tcsr

          - qcom,sm8550-tcsr

          - qcom,sm8650-tcsr

          - qcom,x1e80100-tcsr