Commit af019bef authored by Jack Xiao's avatar Jack Xiao Committed by Alex Deucher
Browse files

drm/amdgpu/gfx11: add aggregated doorbell support 



Port aggregated doorbell support to gfx11.

Signed-off-by: default avatarJack Xiao <Jack.Xiao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 86ef6eae

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+71 −11
Original line number Diff line number Diff line
@@ -5379,14 +5379,45 @@ static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring) 
static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t *wptr_saved;

	uint32_t *is_queue_unmap;

	uint64_t aggregated_db_index;

	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;

	uint64_t wptr_tmp;



	if (ring->is_mes_queue) {

		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);

		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +

					      sizeof(uint32_t));

		aggregated_db_index =

			amdgpu_mes_get_aggregated_doorbell_index(adev,

								 ring->hw_prio);



		wptr_tmp = ring->wptr & ring->buf_mask;

		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);

		*wptr_saved = wptr_tmp;

		/* assume doorbell always being used by mes mapped queue */

		if (*is_queue_unmap) {

			WDOORBELL64(aggregated_db_index, wptr_tmp);

			WDOORBELL64(ring->doorbell_index, wptr_tmp);

		} else {

			WDOORBELL64(ring->doorbell_index, wptr_tmp);



			if (*is_queue_unmap)

				WDOORBELL64(aggregated_db_index, wptr_tmp);

		}

	} else {

		if (ring->use_doorbell) {

			/* XXX check if swapping is necessary on BE */

		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);

			atomic64_set((atomic64_t *)ring->wptr_cpu_addr,

				     ring->wptr);

			WDOORBELL64(ring->doorbell_index, ring->wptr);

		} else {

		WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));

		WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));

			WREG32_SOC15(GC, 0, regCP_RB0_WPTR,

				     lower_32_bits(ring->wptr));

			WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,

				     upper_32_bits(ring->wptr));

		}

	}

}
@@ -5411,15 +5442,44 @@ static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring) 
static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)

{

	struct amdgpu_device *adev = ring->adev;

	uint32_t *wptr_saved;

	uint32_t *is_queue_unmap;

	uint64_t aggregated_db_index;

	uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;

	uint64_t wptr_tmp;



	if (ring->is_mes_queue) {

		wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);

		is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +

					      sizeof(uint32_t));

		aggregated_db_index =

			amdgpu_mes_get_aggregated_doorbell_index(adev,

								 ring->hw_prio);



		wptr_tmp = ring->wptr & ring->buf_mask;

		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);

		*wptr_saved = wptr_tmp;

		/* assume doorbell always used by mes mapped queue */

		if (*is_queue_unmap) {

			WDOORBELL64(aggregated_db_index, wptr_tmp);

			WDOORBELL64(ring->doorbell_index, wptr_tmp);

		} else {

			WDOORBELL64(ring->doorbell_index, wptr_tmp);



			if (*is_queue_unmap)

				WDOORBELL64(aggregated_db_index, wptr_tmp);

		}

	} else {

		/* XXX check if swapping is necessary on BE */

		if (ring->use_doorbell) {

		atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr);

			atomic64_set((atomic64_t *)ring->wptr_cpu_addr,

				     ring->wptr);

			WDOORBELL64(ring->doorbell_index, ring->wptr);

		} else {

			BUG(); /* only DOORBELL method supported on gfx11 now */

		}

	}

}



static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)

{