Commit b2f82401 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and... 

Merge branches 'clk-mobileye', 'clk-twl', 'clk-nuvoton', 'clk-renesas' and 'clk-bindings' into clk-next

 - Mobileye EyeQ5, EyeQ6L and EyeQ6H clk driver
 - TWL6030 clk driver
 - Nuvoton Arbel BMC NPCM8XX SoC clks
 - Convert more clk bindings to YAML

* clk-mobileye:
  clk: eyeq: add EyeQ6H west fixed factor clocks
  clk: eyeq: add EyeQ6H central fixed factor clocks
  clk: eyeq: add EyeQ5 fixed factor clocks
  clk: eyeq: add fixed factor clocks infrastructure
  clk: eyeq: require clock index with phandle in all cases
  clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
  dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks
  dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
  clk: eyeq: add driver
  clk: divider: Introduce CLK_DIVIDER_EVEN_INTEGERS flag
  dt-bindings: clock: add Mobileye EyeQ6L/EyeQ6H clock indexes
  Revert "dt-bindings: clock: mobileye,eyeq5-clk: add bindings"

* clk-twl:
  clk: twl: add TWL6030 support
  clk: twl: remove is_prepared

* clk-nuvoton:
  clk: npcm8xx: add clock controller
  reset: npcm: register npcm8xx clock auxiliary bus device
  dt-bindings: reset: npcm: add clock properties

* clk-renesas:
  clk: renesas: vbattb: Add VBATTB clock driver
  clk: Add devm_clk_hw_register_gate_parent_hw()
  clk: renesas: rzg2l: Fix FOUTPOSTDIV clk
  dt-bindings: clock: renesas,r9a08g045-vbattb: Document VBATTB
  clk: renesas: r9a08g045: Add power domain for RTC
  clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe
  clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones
  clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup()
  dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
  clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks
  clk: renesas: r9a09g057: Add clock and reset entries for ICU
  clk: renesas: r9a09g057: Add CA55 core clocks
  clk: renesas: Remove duplicate and trailing empty lines

* clk-bindings:
  dt-bindings: clock: actions,owl-cmu: convert to YAML
  dt-bindings: clock: ti: Convert mux.txt to json-schema
  dt-bindings: clock: ti: Convert divider.txt to json-schema
  dt-bindings: clock: ti: Convert interface.txt to json-schema
  dt-bindings: clock: convert rockchip,rk3328-cru.txt to YAML
parents 6af88ccf 1cbdfcfd 9abc1eb6 e0b255df 0c159634 53454b7a

Documentation/devicetree/bindings/clock/actions,owl-cmu.txt

deleted100644 → 0
+0 −52
Original line number Diff line number Diff line 
* Actions Semi Owl Clock Management Unit (CMU)



The Actions Semi Owl Clock Management Unit generates and supplies clock

to various controllers within the SoC. The clock binding described here is

applicable to S900, S700 and S500 SoC's.



Required Properties:



- compatible: should be one of the following,

	"actions,s900-cmu"

	"actions,s700-cmu"

	"actions,s500-cmu"

- reg: physical base address of the controller and length of memory mapped

  region.

- clocks: Reference to the parent clocks ("hosc", "losc")

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Each clock is assigned an identifier, and client nodes can use this identifier

to specify the clock which they consume.



All available clocks are defined as preprocessor macros in corresponding

dt-bindings/clock/actions,s900-cmu.h or actions,s700-cmu.h or

actions,s500-cmu.h header and can be used in device tree sources.



External clocks:



The hosc clock used as input for the plls is generated outside the SoC. It is

expected that it is defined using standard clock bindings as "hosc".



Actions Semi S900 CMU also requires one more clock:

 - "losc" - internal low frequency oscillator



Example: Clock Management Unit node:



        cmu: clock-controller@e0160000 {

                compatible = "actions,s900-cmu";

                reg = <0x0 0xe0160000 0x0 0x1000>;

                clocks = <&hosc>, <&losc>;

                #clock-cells = <1>;

                #reset-cells = <1>;

        };



Example: UART controller node that consumes clock generated by the clock

management unit:



        uart: serial@e012a000 {

                compatible = "actions,s900-uart", "actions,owl-uart";

                reg = <0x0 0xe012a000 0x0 0x2000>;

                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

                clocks = <&cmu CLK_UART5>;

        };

Documentation/devicetree/bindings/clock/actions,owl-cmu.yaml

0 → 100644
+60 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/actions,owl-cmu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Actions Semi Owl Clock Management Unit (CMU)



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description: |

  The Actions Semi Owl Clock Management Unit generates and supplies clock

  to various controllers within the SoC.



  See also:

    include/dt-bindings/clock/actions,s500-cmu.h

    include/dt-bindings/clock/actions,s700-cmu.h

    include/dt-bindings/clock/actions,s900-cmu.h



properties:

  compatible:

    enum:

      - actions,s500-cmu

      - actions,s700-cmu

      - actions,s900-cmu



  reg:

    maxItems: 1



  clocks:

    items:

      - description: Host oscillator source

      - description: Internal low frequency oscillator source



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    clock-controller@e0160000 {

        compatible = "actions,s900-cmu";

        reg = <0xe0160000 0x1000>;

        clocks = <&hosc>, <&losc>;

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml

deleted100644 → 0
+0 −51
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mobileye EyeQ5 clock controller



description:

  The EyeQ5 clock controller handles 10 read-only PLLs derived from the main

  crystal clock. It also exposes one divider clock, a child of one of the PLLs.

  Its registers live in a shared region called OLB.



maintainers:

  - Grégory Clement <gregory.clement@bootlin.com>

  - Théo Lebrun <theo.lebrun@bootlin.com>

  - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>



properties:

  compatible:

    const: mobileye,eyeq5-clk



  reg:

    maxItems: 2



  reg-names:

    items:

      - const: plls

      - const: ospi



  "#clock-cells":

    const: 1



  clocks:

    maxItems: 1

    description:

      Input parent clock to all PLLs. Expected to be the main crystal.



  clock-names:

    items:

      - const: ref



required:

  - compatible

  - reg

  - reg-names

  - "#clock-cells"

  - clocks

  - clock-names



additionalProperties: false

Documentation/devicetree/bindings/clock/renesas,r9a08g045-vbattb.yaml

0 → 100644
+84 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,r9a08g045-vbattb.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Renesas Battery Backup Function (VBATTB)



description:

  Renesas VBATTB is an always on powered module (backed by battery) which

  controls the RTC clock (VBATTCLK), tamper detection logic and a small

  general usage memory (128B).



maintainers:

  - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>



properties:

  compatible:

    const: renesas,r9a08g045-vbattb



  reg:

    maxItems: 1



  interrupts:

    items:

      - description: tamper detector interrupt



  clocks:

    items:

      - description: VBATTB module clock

      - description: RTC input clock (crystal or external clock device)



  clock-names:

    items:

      - const: bclk

      - const: rtx



  '#clock-cells':

    const: 1



  power-domains:

    maxItems: 1



  resets:

    items:

      - description: VBATTB module reset



  quartz-load-femtofarads:

    description: load capacitance of the on board crystal

    enum: [ 4000, 7000, 9000, 12500 ]

    default: 4000



required:

  - compatible

  - reg

  - interrupts

  - clocks

  - clock-names

  - '#clock-cells'

  - power-domains

  - resets



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/r9a08g045-cpg.h>

    #include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/interrupt-controller/irq.h>



    clock-controller@1005c000 {

        compatible = "renesas,r9a08g045-vbattb";

        reg = <0x1005c000 0x1000>;

        interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>;

        clock-names = "bclk", "rtx";

        assigned-clocks = <&vbattb VBATTB_MUX>;

        assigned-clock-parents = <&vbattb VBATTB_XC>;

        #clock-cells = <1>;

        power-domains = <&cpg>;

        resets = <&cpg R9A08G045_VBAT_BRESETN>;

        quartz-load-femtofarads = <12500>;

    };

Documentation/devicetree/bindings/clock/rockchip,rk3328-cru.txt

deleted100644 → 0
+0 −58
Original line number Diff line number Diff line 
* Rockchip RK3328 Clock and Reset Unit



The RK3328 clock controller generates and supplies clock to various

controllers within the SoC and also implements a reset controller for SoC

peripherals.



Required Properties:



- compatible: should be "rockchip,rk3328-cru"

- reg: physical base address of the controller and length of memory mapped

  region.

- #clock-cells: should be 1.

- #reset-cells: should be 1.



Optional Properties:



- rockchip,grf: phandle to the syscon managing the "general register files"

  If missing pll rates are not changeable, due to the missing pll lock status.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/rk3328-cru.h headers and can be

used in device tree sources. Similar macros exist for the reset sources in

these files.



External clocks:



There are several clocks that are generated outside the SoC. It is expected

that they are defined using standard clock bindings with following

clock-output-names:

 - "xin24m" - crystal input - required,

 - "clkin_i2s" - external I2S clock - optional,

 - "gmac_clkin" - external GMAC clock - optional

 - "phy_50m_out" - output clock of the pll in the mac phy

 - "hdmi_phy" - output clock of the hdmi phy pll - optional



Example: Clock controller node:



	cru: clock-controller@ff440000 {

		compatible = "rockchip,rk3328-cru";

		reg = <0x0 0xff440000 0x0 0x1000>;

		rockchip,grf = <&grf>;



		#clock-cells = <1>;

		#reset-cells = <1>;

	};



Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart0: serial@ff120000 {

		compatible = "snps,dw-apb-uart";

		reg = <0xff120000 0x100>;

		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;

		reg-shift = <2>;

		reg-io-width = <4>;

		clocks = <&cru SCLK_UART0>;

	};