Unverified Commit b616b403 authored by Rafał Miłecki's avatar Rafał Miłecki Committed by AngeloGioacchino Del Regno
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arm64: dts: mediatek: mt7988: add clock controllers 



Add bindings of on-SoC clocks.

Signed-off-by: default avatarRafał Miłecki <rafal@milecki.pl>
Reviewed-by: default avatarDaniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20240108085228.4727-4-zajec5@gmail.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent 6c1d134a

arch/arm64/boot/dts/mediatek/mt7988a.dtsi

+40 −1
Original line number Diff line number Diff line
@@ -78,12 +78,51 @@ gic: interrupt-controller@c000000 { 
			#interrupt-cells = <3>;

		};



		watchdog@1001c000 {

		clock-controller@10001000 {

			compatible = "mediatek,mt7988-infracfg", "syscon";

			reg = <0 0x10001000 0 0x1000>;

			#clock-cells = <1>;

		};



		clock-controller@1001b000 {

			compatible = "mediatek,mt7988-topckgen", "syscon";

			reg = <0 0x1001b000 0 0x1000>;

			#clock-cells = <1>;

		};



		watchdog: watchdog@1001c000 {

			compatible = "mediatek,mt7988-wdt";

			reg = <0 0x1001c000 0 0x1000>;

			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;

			#reset-cells = <1>;

		};



		clock-controller@1001e000 {

			compatible = "mediatek,mt7988-apmixedsys";

			reg = <0 0x1001e000 0 0x1000>;

			#clock-cells = <1>;

		};



		clock-controller@11f40000 {

			compatible = "mediatek,mt7988-xfi-pll";

			reg = <0 0x11f40000 0 0x1000>;

			resets = <&watchdog 16>;

			#clock-cells = <1>;

		};



		clock-controller@15000000 {

			compatible = "mediatek,mt7988-ethsys", "syscon";

			reg = <0 0x15000000 0 0x1000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

		};



		clock-controller@15031000 {

			compatible = "mediatek,mt7988-ethwarp";

			reg = <0 0x15031000 0 0x1000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

		};

	};



	timer {