Commit beb2e446 authored by Sean Christopherson's avatar Sean Christopherson
Browse files

x86/cpu: KVM: Move macro to encode PAT value to common header 



Move pat/memtype.c's PAT() macro to msr-index.h as PAT_VALUE(), and use it
in KVM to define the default (Power-On / RESET) PAT value instead of open
coding an inscrutable magic number.

No functional change intended.

Reviewed-by: default avatarXiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: default avatarKai Huang <kai.huang@intel.com>
Reviewed-by: default avatarThomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20240605231918.2915961-3-seanjc@google.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent e7e80b66

arch/x86/include/asm/msr-index.h

+6 −0
Original line number Diff line number Diff line
@@ -377,6 +377,12 @@ 


#define MSR_IA32_CR_PAT			0x00000277



#define PAT_VALUE(p0, p1, p2, p3, p4, p5, p6, p7)			\

	((X86_MEMTYPE_ ## p0)      | (X86_MEMTYPE_ ## p1 << 8)  |	\

	(X86_MEMTYPE_ ## p2 << 16) | (X86_MEMTYPE_ ## p3 << 24) |	\

	(X86_MEMTYPE_ ## p4 << 32) | (X86_MEMTYPE_ ## p5 << 40) |	\

	(X86_MEMTYPE_ ## p6 << 48) | (X86_MEMTYPE_ ## p7 << 56))



#define MSR_IA32_DEBUGCTLMSR		0x000001d9

#define MSR_IA32_LASTBRANCHFROMIP	0x000001db

#define MSR_IA32_LASTBRANCHTOIP		0x000001dc

arch/x86/kvm/x86.h

+2 −1
Original line number Diff line number Diff line
@@ -103,7 +103,8 @@ static inline unsigned int __shrink_ple_window(unsigned int val, 
	return max(val, min);

}



#define MSR_IA32_CR_PAT_DEFAULT  0x0007040600070406ULL

#define MSR_IA32_CR_PAT_DEFAULT	\

	PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC)



void kvm_service_local_tlb_flush_requests(struct kvm_vcpu *vcpu);

int kvm_check_nested_events(struct kvm_vcpu *vcpu);

arch/x86/mm/pat/memtype.c

+3 −10
Original line number Diff line number Diff line
@@ -248,12 +248,6 @@ void pat_cpu_init(void) 
void __init pat_bp_init(void)

{

	struct cpuinfo_x86 *c = &boot_cpu_data;

#define PAT(p0, p1, p2, p3, p4, p5, p6, p7)				\

	((X86_MEMTYPE_ ## p0)      | (X86_MEMTYPE_ ## p1 << 8)  |	\

	(X86_MEMTYPE_ ## p2 << 16) | (X86_MEMTYPE_ ## p3 << 24) |	\

	(X86_MEMTYPE_ ## p4 << 32) | (X86_MEMTYPE_ ## p5 << 40) |	\

	(X86_MEMTYPE_ ## p6 << 48) | (X86_MEMTYPE_ ## p7 << 56))





	if (!IS_ENABLED(CONFIG_X86_PAT))

		pr_info_once("x86/PAT: PAT support disabled because CONFIG_X86_PAT is disabled in the kernel.\n");
@@ -284,7 +278,7 @@ void __init pat_bp_init(void) 
		 * NOTE: When WC or WP is used, it is redirected to UC- per

		 * the default setup in __cachemode2pte_tbl[].

		 */

		pat_msr_val = PAT(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC);

		pat_msr_val = PAT_VALUE(WB, WT, UC_MINUS, UC, WB, WT, UC_MINUS, UC);

	}



	/*
@@ -319,7 +313,7 @@ void __init pat_bp_init(void) 
		 * NOTE: When WT or WP is used, it is redirected to UC- per

		 * the default setup in __cachemode2pte_tbl[].

		 */

		pat_msr_val = PAT(WB, WC, UC_MINUS, UC, WB, WC, UC_MINUS, UC);

		pat_msr_val = PAT_VALUE(WB, WC, UC_MINUS, UC, WB, WC, UC_MINUS, UC);

	} else {

		/*

		 * Full PAT support.  We put WT in slot 7 to improve
@@ -347,13 +341,12 @@ void __init pat_bp_init(void) 
		 * The reserved slots are unused, but mapped to their

		 * corresponding types in the presence of PAT errata.

		 */

		pat_msr_val = PAT(WB, WC, UC_MINUS, UC, WB, WP, UC_MINUS, WT);

		pat_msr_val = PAT_VALUE(WB, WC, UC_MINUS, UC, WB, WP, UC_MINUS, WT);

	}



	memory_caching_control |= CACHE_PAT;



	init_cache_modes(pat_msr_val);

#undef PAT

}



static DEFINE_SPINLOCK(memtype_lock);	/* protects memtype accesses */