Commit bf0fd737 authored by Uma Shankar's avatar Uma Shankar Committed by Jani Nikula
Browse files

drm/i915/color: Program Plane Post CSC Registers 



Extract the LUT and program plane post csc registers.

v2: Add DSB support
v3: Add support for single segment 1D LUT
v4:
- s/drm_color_lut_32/drm_color_lut32 (Simon)
- Move declaration to beginning of the function (Suraj)
- Remove multisegmented code, add it later
- Remove dead code for SDR planes, add it later
v5:
- Fix iterator issues
v6: Removed redundant variable (Suraj)

Reviewed-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarChaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Link: https://patch.msgid.link/20251203085211.3663374-13-uma.shankar@intel.com


Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 82caa1c8

drivers/gpu/drm/i915/display/intel_color.c

+59 −0
Original line number Diff line number Diff line
@@ -3996,11 +3996,70 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, 
	}

}



static void

xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb,

				 const struct intel_plane_state *plane_state)

{

	struct intel_display *display = to_intel_display(plane_state);

	const struct drm_plane_state *state = &plane_state->uapi;

	enum pipe pipe = to_intel_plane(state->plane)->pipe;

	enum plane_id plane = to_intel_plane(state->plane)->id;

	const struct drm_color_lut32 *post_csc_lut = plane_state->hw.gamma_lut->data;

	u32 i, lut_size, lut_val;



	if (icl_is_hdr_plane(display, plane)) {

		intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0),

				   PLANE_PAL_PREC_AUTO_INCREMENT);

		/* TODO: Add macro */

		intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0),

				   PLANE_PAL_PREC_AUTO_INCREMENT);

		if (post_csc_lut) {

			lut_size = 32;

			for (i = 0; i < lut_size; i++) {

				lut_val = drm_color_lut32_extract(post_csc_lut[i].green, 24);



				intel_de_write_dsb(display, dsb,

						   PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),

						   lut_val);

			}



			/* Segment 2 */

			do {

				intel_de_write_dsb(display, dsb,

						   PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),

						   (1 << 24));

			} while (i++ < 34);

		} else {

			/*TODO: Add for segment 0 */

			lut_size = 32;

			for (i = 0; i < lut_size; i++) {

				u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);



				intel_de_write_dsb(display, dsb,

						   PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), v);

			}



			do {

				intel_de_write_dsb(display, dsb,

						   PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0),

						   1 << 24);

			} while (i++ < 34);

		}



		intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0);

		intel_de_write_dsb(display, dsb,

				   PLANE_POST_CSC_GAMC_SEG0_INDEX_ENH(pipe, plane, 0), 0);

	}

}



static void

xelpd_plane_load_luts(struct intel_dsb *dsb, const struct intel_plane_state *plane_state)

{

	if (plane_state->hw.degamma_lut)

		xelpd_program_plane_pre_csc_lut(dsb, plane_state);



	if (plane_state->hw.gamma_lut)

		xelpd_program_plane_post_csc_lut(dsb, plane_state);

}



static const struct intel_color_funcs chv_color_funcs = {