Commit c44d4ef4 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xelpg: Extend some workarounds/tuning to gfx version 12.74 



Some of our existing Xe_LPG workarounds and tuning are also applicable
to the version 12.74 variant.  Extend the condition bounds accordingly.
Also fix the comment on Wa_14018575942 while we're at it.

v2: Extend some more workarounds (Harish)

Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarHarish Chegondi <harish.chegondi@intel.com>
Signed-off-by: default avatarHaridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240108122738.14399-4-haridhar.kalvala@intel.com
parent 84bf82f4

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+2 −2
Original line number Diff line number Diff line
@@ -226,7 +226,7 @@ u32 *gen12_emit_aux_table_inv(struct intel_engine_cs *engine, u32 *cs) 
static int mtl_dummy_pipe_control(struct i915_request *rq)

{

	/* Wa_14016712196 */

	if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 71)) ||

	if (IS_GFX_GT_IP_RANGE(rq->engine->gt, IP_VER(12, 70), IP_VER(12, 74)) ||

	    IS_DG2(rq->i915)) {

		u32 *cs;
@@ -822,7 +822,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 
		flags |= PIPE_CONTROL_FLUSH_L3;



	/* Wa_14016712196 */

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))

		/* dummy PIPE_CONTROL + depth flush */

		cs = gen12_emit_pipe_control(cs, 0,

					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);

drivers/gpu/drm/i915/gt/intel_workarounds.c

+15 −9
Original line number Diff line number Diff line
@@ -789,8 +789,13 @@ static void xelpg_ctx_gt_tuning_init(struct intel_engine_cs *engine, 


	dg2_ctx_gt_tuning_init(engine, wal);



	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||

	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))

	/*

	 * Due to Wa_16014892111, the DRAW_WATERMARK tuning must be done in

	 * gen12_emit_indirect_ctx_rcs() rather than here on some early

	 * steppings.

	 */

	if (!(IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||

	      IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)))

		wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);

}
@@ -911,7 +916,7 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine, 
	if (engine->class != RENDER_CLASS)

		goto done;



	if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))

	if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))

		xelpg_ctx_workarounds_init(engine, wal);

	else if (IS_PONTEVECCHIO(i915))

		; /* noop; none at this time */
@@ -1646,7 +1651,7 @@ pvc_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
static void

xelpg_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)

{

	/* Wa_14018778641 / Wa_18018781329 */

	/* Wa_14018575942 / Wa_18018781329 */

	wa_mcr_write_or(wal, COMP_MOD_CTRL, FORCE_MISS_FTLB);



	/* Wa_22016670082 */
@@ -1713,7 +1718,7 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal) 
 */

static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)

{

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {

		wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);

		wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);

	}
@@ -1746,7 +1751,7 @@ gt_init_workarounds(struct intel_gt *gt, struct i915_wa_list *wal) 
		return;

	}



	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))

		xelpg_gt_workarounds_init(gt, wal);

	else if (IS_PONTEVECCHIO(i915))

		pvc_gt_workarounds_init(gt, wal);
@@ -2219,7 +2224,7 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine) 


	if (engine->gt->type == GT_MEDIA)

		; /* none yet */

	else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))

	else if (IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 74)))

		xelpg_whitelist_build(engine);

	else if (IS_PONTEVECCHIO(i915))

		pvc_whitelist_build(engine);
@@ -2831,7 +2836,7 @@ add_render_compute_tuning_settings(struct intel_gt *gt, 
{

	struct drm_i915_private *i915 = gt->i915;



	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)) || IS_DG2(i915))

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)) || IS_DG2(i915))

		wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);



	/*
@@ -2884,7 +2889,8 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li 
	}



	if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) ||

	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER))

	    IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER) ||

	    IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 74), IP_VER(12, 74)))

		/* Wa_14017856879 */

		wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH);

drivers/gpu/drm/i915/i915_perf.c

+1 −1
Original line number Diff line number Diff line
@@ -3225,7 +3225,7 @@ u32 i915_perf_oa_timestamp_frequency(struct drm_i915_private *i915) 
	struct intel_gt *gt = to_gt(i915);



	/* Wa_18013179988 */

	if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71))) {

	if (IS_DG2(i915) || IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74))) {

		intel_wakeref_t wakeref;

		u32 reg, shift;