Commit ca39a371 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-gt-next-2025-07-02' of... 

Merge tag 'drm-intel-gt-next-2025-07-02' of https://gitlab.freedesktop.org/drm/i915/kernel

 into drm-next

Driver Changes:

Fixes/improvements/new stuff:

- Avoid GuC scheduling stalls [guc] (Julia Filipchuk)
- Remove force_probe requirement for DG1 (Ville Syrjälä)
- Handle errors correctly to avoid losing GuC-2-Host messages [guc] (Jesus Narvaez)
- Avoid double wakeref put if GuC context deregister failed [guc] (Jesus Narvaez)
- Avoid timeline memory leak with signals and legacy platforms [ringbuf] (Janusz Krzysztofik)
- Fix MEI (discrete) interrupt handler on RT kernels [gsc] (Junxiao Chang)

Miscellaneous:

- Allow larger memory allocation [selftest] (Mikolaj Wasiak)
- Use provided dma_fence_is_chain (Tvrtko Ursulin)
- Fix build error with GCOV and AutoFDO enabled [pmu] (Tzung-Bi Shih)
- Fix build error some more (Arnd Bergmann)
- Reduce stack usage in igt_vma_pin1() (Arnd Bergmann)
- Move out engine related macros from i915_drv.h (Krzysztof Karas)
- Move GEM_QUIRK_PIN_SWIZZLED_PAGES to i915_gem.h (Krzysztof Karas)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Tvrtko Ursulin <tursulin@igalia.com>
Link: https://lore.kernel.org/r/aGTjUBeOQFw26bRT@linux
parents 7e281838 dccf655f

drivers/gpu/drm/i915/gem/i915_gem_wait.c

+1 −6
Original line number Diff line number Diff line
@@ -106,11 +106,6 @@ static void fence_set_priority(struct dma_fence *fence, 
	rcu_read_unlock();

}



static inline bool __dma_fence_is_chain(const struct dma_fence *fence)

{

	return fence->ops == &dma_fence_chain_ops;

}



void i915_gem_fence_wait_priority(struct dma_fence *fence,

				  const struct i915_sched_attr *attr)

{
@@ -126,7 +121,7 @@ void i915_gem_fence_wait_priority(struct dma_fence *fence, 


		for (i = 0; i < array->num_fences; i++)

			fence_set_priority(array->fences[i], attr);

	} else if (__dma_fence_is_chain(fence)) {

	} else if (dma_fence_is_chain(fence)) {

		struct dma_fence *iter;



		/* The chain is ordered; if we boost the last, we boost all */

drivers/gpu/drm/i915/gt/intel_engine.h

+31 −0
Original line number Diff line number Diff line
@@ -79,6 +79,29 @@ struct lock_class_key; 
#define ENGINE_WRITE(...)	__ENGINE_WRITE_OP(write, __VA_ARGS__)

#define ENGINE_WRITE_FW(...)	__ENGINE_WRITE_OP(write_fw, __VA_ARGS__)



#define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))

#define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)



#define __ENGINE_INSTANCES_MASK(mask, first, count) ({			\

	unsigned int first__ = (first);					\

	unsigned int count__ = (count);					\

	((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__;	\

})



#define ENGINE_INSTANCES_MASK(gt, first, count) \

	__ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)



#define RCS_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)

#define BCS_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)

#define VDBOX_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)

#define VEBOX_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)

#define CCS_MASK(gt) \

	ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)



#define GEN6_RING_FAULT_REG_READ(engine__) \

	intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
@@ -355,4 +378,12 @@ u64 intel_clamp_preempt_timeout_ms(struct intel_engine_cs *engine, u64 value); 
u64 intel_clamp_stop_timeout_ms(struct intel_engine_cs *engine, u64 value);

u64 intel_clamp_timeslice_duration_ms(struct intel_engine_cs *engine, u64 value);



#define rb_to_uabi_engine(rb) \

	rb_entry_safe(rb, struct intel_engine_cs, uabi_node)



#define for_each_uabi_engine(engine__, i915__) \

	for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\

	     (engine__); \

	     (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))



#endif /* _INTEL_RINGBUFFER_H_ */

drivers/gpu/drm/i915/gt/intel_gsc.c

+1 −1
Original line number Diff line number Diff line
@@ -284,7 +284,7 @@ static void gsc_irq_handler(struct intel_gt *gt, unsigned int intf_id) 
	if (gt->gsc.intf[intf_id].irq < 0)

		return;



	ret = generic_handle_irq(gt->gsc.intf[intf_id].irq);

	ret = generic_handle_irq_safe(gt->gsc.intf[intf_id].irq);

	if (ret)

		gt_err_ratelimited(gt, "error handling GSC irq: %d\n", ret);

}

drivers/gpu/drm/i915/gt/intel_ring_submission.c

+2 −1
Original line number Diff line number Diff line
@@ -610,7 +610,6 @@ static int ring_context_alloc(struct intel_context *ce) 
	/* One ringbuffer to rule them all */

	GEM_BUG_ON(!engine->legacy.ring);

	ce->ring = engine->legacy.ring;

	ce->timeline = intel_timeline_get(engine->legacy.timeline);



	GEM_BUG_ON(ce->state);

	if (engine->context_size) {
@@ -623,6 +622,8 @@ static int ring_context_alloc(struct intel_context *ce) 
		ce->state = vma;

	}



	ce->timeline = intel_timeline_get(engine->legacy.timeline);



	return 0;

}

drivers/gpu/drm/i915/gt/uc/intel_guc.c

+6 −1
Original line number Diff line number Diff line
@@ -313,8 +313,13 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) 
	 *

	 * The same WA bit is used for both and 22011391025 is applicable to

	 * all DG2.

	 *

	 * Platforms post DG2 prevent this issue in hardware by stalling

	 * submissions. With this flag GuC will schedule as to avoid such

	 * stalls.

	 */

	if (IS_DG2(gt->i915))

	if (IS_DG2(gt->i915) ||

	    (CCS_MASK(gt) && GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70)))

		flags |= GUC_WA_DUAL_QUEUE;



	/* Wa_22011802037: graphics version 11/12 */