Commit cf3f100c authored by Lijo Lazar's avatar Lijo Lazar Committed by Alex Deucher
Browse files

drm/amd/pm: Use message control for debug mailbox 



Migrate existing debug message mechanism so that it uses debug message
callbacks in message control block.

Signed-off-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarAsad Kamal <asad.kamal@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2f0d5eca

drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h

+0 −4
Original line number Diff line number Diff line
@@ -755,10 +755,6 @@ struct smu_context { 


	struct firmware pptable_firmware;



	u32 debug_param_reg;

	u32 debug_msg_reg;

	u32 debug_resp_reg;



	struct delayed_work		swctf_delayed_work;



	/* data structures for wbrf feature support */

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c

+1 −0
Original line number Diff line number Diff line
@@ -2366,6 +2366,7 @@ void smu_v13_0_init_msg_ctl(struct smu_context *smu, 
	ctl->ops = &smu_msg_v1_ops;

	ctl->default_timeout = adev->usec_timeout * 20;

	ctl->message_map = message_map;

	ctl->flags = 0;

}



int smu_v13_0_mode1_reset(struct smu_context *smu)

drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c

+10 −6
Original line number Diff line number Diff line
@@ -2882,13 +2882,18 @@ static int smu_v13_0_0_enable_gfx_features(struct smu_context *smu) 
		return -EOPNOTSUPP;

}



static void smu_v13_0_0_set_smu_mailbox_registers(struct smu_context *smu)

static void smu_v13_0_0_init_msg_ctl(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;

	struct smu_msg_ctl *ctl = &smu->msg_ctl;



	smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);

	smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);

	smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);

	smu_v13_0_init_msg_ctl(smu, smu_v13_0_0_message_map);



	/* Set up debug mailbox registers */

	ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_53);

	ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_75);

	ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);

	ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX;

}



static int smu_v13_0_0_smu_send_bad_mem_page_num(struct smu_context *smu,
@@ -3216,8 +3221,7 @@ void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu) 
	smu->pwr_src_map = smu_v13_0_0_pwr_src_map;

	smu->workload_map = smu_v13_0_0_workload_map;

	smu->smc_driver_if_version = SMU13_0_0_DRIVER_IF_VERSION;

	smu_v13_0_0_set_smu_mailbox_registers(smu);

	smu_v13_0_init_msg_ctl(smu, smu_v13_0_0_message_map);

	smu_v13_0_0_init_msg_ctl(smu);



	if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==

		IP_VERSION(13, 0, 10) &&

drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

+7 −10
Original line number Diff line number Diff line
@@ -2107,15 +2107,6 @@ static int smu_v14_0_2_enable_gfx_features(struct smu_context *smu) 
		return -EOPNOTSUPP;

}



static void smu_v14_0_2_set_smu_mailbox_registers(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;



	smu->debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53);

	smu->debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75);

	smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54);

}



static void smu_v14_0_2_init_msg_ctl(struct smu_context *smu)

{

	struct amdgpu_device *adev = smu->adev;
@@ -2130,6 +2121,13 @@ static void smu_v14_0_2_init_msg_ctl(struct smu_context *smu) 
	ctl->ops = &smu_msg_v1_ops;

	ctl->default_timeout = adev->usec_timeout * 20;

	ctl->message_map = smu_v14_0_2_message_map;

	ctl->flags = 0;



	/* Set up debug mailbox registers */

	ctl->config.debug_param_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_53);

	ctl->config.debug_msg_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_75);

	ctl->config.debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54);

	ctl->flags |= SMU_MSG_CTL_DEBUG_MAILBOX;

}



static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu,
@@ -2876,6 +2874,5 @@ void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu) 
	smu->table_map = smu_v14_0_2_table_map;

	smu->pwr_src_map = smu_v14_0_2_pwr_src_map;

	smu->workload_map = smu_v14_0_2_workload_map;

	smu_v14_0_2_set_smu_mailbox_registers(smu);

	smu_v14_0_2_init_msg_ctl(smu);

}

drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c

+8 −11
Original line number Diff line number Diff line
@@ -102,17 +102,14 @@ static int smu_msg_v1_send_debug_msg(struct smu_msg_ctl *ctl, u32 msg, u32 param 
	return 0;

}



static int __smu_cmn_send_debug_msg(struct smu_context *smu,

static int __smu_cmn_send_debug_msg(struct smu_msg_ctl *ctl,

				    u32 msg,

				    u32 param)

{

	struct amdgpu_device *adev = smu->adev;



	WREG32(smu->debug_param_reg, param);

	WREG32(smu->debug_msg_reg, msg);

	WREG32(smu->debug_resp_reg, 0);

	if (!ctl->ops || !ctl->ops->send_debug_msg)

		return -EOPNOTSUPP;



	return 0;

	return ctl->ops->send_debug_msg(ctl, msg, param);

}



/**
@@ -199,13 +196,13 @@ int smu_cmn_send_smc_msg(struct smu_context *smu, 
int smu_cmn_send_debug_smc_msg(struct smu_context *smu,

			 uint32_t msg)

{

	return __smu_cmn_send_debug_msg(smu, msg, 0);

	return __smu_cmn_send_debug_msg(&smu->msg_ctl, msg, 0);

}



int smu_cmn_send_debug_smc_msg_with_param(struct smu_context *smu,

			 uint32_t msg, uint32_t param)

{

	return __smu_cmn_send_debug_msg(smu, msg, param);

	return __smu_cmn_send_debug_msg(&smu->msg_ctl, msg, param);

}



static int smu_msg_v1_decode_response(u32 resp)