Commit d6a8336c authored by Jouni Högander's avatar Jouni Högander
Browse files

drm/i915/alpm: Write PR_ALPM_CTL register 



PR_ALPM_CTL register contains configurations related to Adaptive sync
sdp. Configure these if Adaptive Sync SDP is supported.

v2: avoid using hardcoded indices

Bspec: 71014
Signed-off-by: default avatarJouni Högander <jouni.hogander@intel.com>
Reviewed-by: default avatarAnkit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://lore.kernel.org/r/20250526120512.1702815-6-jouni.hogander@intel.com
parent 91a2cd62

drivers/gpu/drm/i915/display/intel_alpm.c

+14 −0
Original line number Diff line number Diff line
@@ -348,6 +348,20 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, 
			ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS |

			ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines);



		if (intel_dp->as_sdp_supported) {

			u32 pr_alpm_ctl = PR_ALPM_CTL_ADAPTIVE_SYNC_SDP_POSITION_T1;



			if (intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &

			    DP_PANEL_REPLAY_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPTIVE_SYNC_SDP)

				pr_alpm_ctl |= PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU;

			if (!(intel_dp->pr_dpcd[INTEL_PR_DPCD_INDEX(DP_PANEL_REPLAY_CAP_CAPABILITY)] &

						DP_PANEL_REPLAY_ASYNC_VIDEO_TIMING_NOT_SUPPORTED_IN_PR))

				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;



			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),

				       pr_alpm_ctl);

		}



		intel_de_write(display,

			       PORT_ALPM_CTL(port),

			       PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE |