Unverified Commit de8f8282 authored by Andy Chiu's avatar Andy Chiu Committed by Palmer Dabbelt
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riscv: hwprobe: add zve Vector subextensions into hwprobe interface 



The following Vector subextensions for "embedded" platforms are added
into RISCV_HWPROBE_KEY_IMA_EXT_0:
 - ZVE32X
 - ZVE32F
 - ZVE64X
 - ZVE64F
 - ZVE64D

Extensions ending with an X indicates that the platform doesn't have a
vector FPU.
Extensions ending with F/D mean that whether single (F) or double (D)
precision vector operation is supported.
The number 32 or 64 follows from ZVE tells the maximum element length.

Signed-off-by: default avatarAndy Chiu <andy.chiu@sifive.com>
Reviewed-by: default avatarClément Léger <cleger@rivosinc.com>
Link: https://lore.kernel.org/r/20240510-zve-detection-v5-6-0711bdd26c12@sifive.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 1e748354

Documentation/arch/riscv/hwprobe.rst

+15 −0
Original line number Diff line number Diff line
@@ -192,6 +192,21 @@ The following keys are defined: 
       supported as defined in the RISC-V ISA manual starting from commit

       d8ab5c78c207 ("Zihintpause is ratified").



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+5 −0
Original line number Diff line number Diff line
@@ -60,6 +60,11 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZACAS		(1ULL << 34)

#define		RISCV_HWPROBE_EXT_ZICOND	(1ULL << 35)

#define		RISCV_HWPROBE_EXT_ZIHINTPAUSE	(1ULL << 36)

#define		RISCV_HWPROBE_EXT_ZVE32X	(1ULL << 37)

#define		RISCV_HWPROBE_EXT_ZVE32F	(1ULL << 38)

#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 39)

#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 40)

#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 41)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_hwprobe.c

+5 −0
Original line number Diff line number Diff line
@@ -114,6 +114,11 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZIHINTPAUSE);



		if (has_vector()) {

			EXT_KEY(ZVE32X);

			EXT_KEY(ZVE32F);

			EXT_KEY(ZVE64X);

			EXT_KEY(ZVE64F);

			EXT_KEY(ZVE64D);

			EXT_KEY(ZVBB);

			EXT_KEY(ZVBC);

			EXT_KEY(ZVKB);