Commit deac9ad4 authored by Peter Griffin's avatar Peter Griffin Committed by Martin K. Petersen
Browse files

scsi: ufs: exynos: Enable PRDT pre-fetching with UFSHCD_CAP_CRYPTO 



PRDT_PREFETCH_ENABLE[31] bit should be set when desctype field of
fmpsecurity0 register is type2 (double file encryption) or type3
(support for file and disk encryption). Setting this bit enables PRDT
pre-fetching on both TXPRDT and RXPRDT.

Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250319-exynos-ufs-stability-fixes-v2-5-96722cc2ba1b@linaro.org


Reviewed-by: default avatarBart Van Assche <bvanassche@acm.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 7f05fd9a

drivers/ufs/host/ufs-exynos.c

+7 −2
Original line number Diff line number Diff line
@@ -34,7 +34,7 @@ 
 * Exynos's Vendor specific registers for UFSHCI

 */

#define HCI_TXPRDT_ENTRY_SIZE	0x00

#define PRDT_PREFECT_EN		BIT(31)

#define PRDT_PREFETCH_EN	BIT(31)

#define HCI_RXPRDT_ENTRY_SIZE	0x04

#define HCI_1US_TO_CNT_VAL	0x0C

#define CNT_VAL_1US_MASK	0x3FF
@@ -1098,12 +1098,17 @@ static int exynos_ufs_post_link(struct ufs_hba *hba) 
	struct exynos_ufs *ufs = ufshcd_get_variant(hba);

	struct phy *generic_phy = ufs->phy;

	struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;

	u32 val = ilog2(DATA_UNIT_SIZE);



	exynos_ufs_establish_connt(ufs);

	exynos_ufs_fit_aggr_timeout(ufs);



	hci_writel(ufs, 0xa, HCI_DATA_REORDER);

	hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_TXPRDT_ENTRY_SIZE);



	if (hba->caps & UFSHCD_CAP_CRYPTO)

		val |= PRDT_PREFETCH_EN;

	hci_writel(ufs, val, HCI_TXPRDT_ENTRY_SIZE);



	hci_writel(ufs, ilog2(DATA_UNIT_SIZE), HCI_RXPRDT_ENTRY_SIZE);

	hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE);

	hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE);