Commit e56272f2 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Vinod Koul
Browse files

phy: airoha: Fix REG_CSR_2L_RX{0,1}_REV0 definitions 



Fix the following register definitions for REG_CSR_2L_RX{0,1}_REV0
registers:
- CSR_2L_PXP_VOS_PNINV
- CSR_2L_PXP_FE_GAIN_NORMAL_MODE
- CSR_2L_PXP_FE_GAIN_TRAIN_MODE

Fixes: d7d2818b ("phy: airoha: Add PCIe PHY driver for EN7581 SoC.")
Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/20240918-airoha-en7581-phy-fixes-v1-4-8291729a87f8@kernel.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 6fd016c9

drivers/phy/phy-airoha-pcie-regs.h

+3 −3
Original line number Diff line number Diff line
@@ -197,9 +197,9 @@ 
#define CSR_2L_PXP_TX1_MULTLANE_EN		BIT(0)



#define REG_CSR_2L_RX0_REV0			0x00fc

#define CSR_2L_PXP_VOS_PNINV			GENMASK(3, 2)

#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE		GENMASK(6, 4)

#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE		GENMASK(10, 8)

#define CSR_2L_PXP_VOS_PNINV			GENMASK(19, 18)

#define CSR_2L_PXP_FE_GAIN_NORMAL_MODE		GENMASK(22, 20)

#define CSR_2L_PXP_FE_GAIN_TRAIN_MODE		GENMASK(26, 24)



#define REG_CSR_2L_RX0_PHYCK_DIV		0x0100

#define CSR_2L_PXP_RX0_PHYCK_SEL		GENMASK(9, 8)