Commit f661eb5f authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/misc' into for-next/core 

* for-next/misc:
  arm64: hibernate: Fix warning for cast from restricted gfp_t
  arm64: esr: Define ESR_ELx_EC_* constants as UL
  arm64: Constify struct kobj_type
  arm64: smp: smp_send_stop() and crash_smp_send_stop() should try non-NMI first
  arm64/sve: Remove unused declaration read_smcr_features()
  arm64: mm: Remove unused declaration early_io_map()
  arm64: el2_setup.h: Rename some labels to be more diff-friendly
  arm64: signal: Fix some under-bracketed UAPI macros
  arm64/mm: Drop TCR_SMP_FLAGS
  arm64/mm: Drop PMD_SECT_VALID
parents dd22f444 ecdd16df

arch/arm64/include/asm/el2_setup.h

+10 −7
Original line number Diff line number Diff line
@@ -165,42 +165,45 @@ 
	mrs	x1, id_aa64dfr0_el1

	ubfx	x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4

	cmp	x1, #3

	b.lt	.Lset_debug_fgt_\@

	b.lt	.Lskip_spe_fgt_\@

	/* Disable PMSNEVFR_EL1 read and write traps */

	orr	x0, x0, #(1 << 62)



.Lset_debug_fgt_\@:

.Lskip_spe_fgt_\@:

	msr_s	SYS_HDFGRTR_EL2, x0

	msr_s	SYS_HDFGWTR_EL2, x0



	mov	x0, xzr

	mrs	x1, id_aa64pfr1_el1

	ubfx	x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4

	cbz	x1, .Lset_pie_fgt_\@

	cbz	x1, .Lskip_debug_fgt_\@



	/* Disable nVHE traps of TPIDR2 and SMPRI */

	orr	x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK

	orr	x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK



.Lset_pie_fgt_\@:

.Lskip_debug_fgt_\@:

	mrs_s	x1, SYS_ID_AA64MMFR3_EL1

	ubfx	x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4

	cbz	x1, .Lset_fgt_\@

	cbz	x1, .Lskip_pie_fgt_\@



	/* Disable trapping of PIR_EL1 / PIRE0_EL1 */

	orr	x0, x0, #HFGxTR_EL2_nPIR_EL1

	orr	x0, x0, #HFGxTR_EL2_nPIRE0_EL1



.Lset_fgt_\@:

.Lskip_pie_fgt_\@:

	msr_s	SYS_HFGRTR_EL2, x0

	msr_s	SYS_HFGWTR_EL2, x0

	msr_s	SYS_HFGITR_EL2, xzr



	mrs	x1, id_aa64pfr0_el1		// AMU traps UNDEF without AMU

	ubfx	x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4

	cbz	x1, .Lskip_fgt_\@

	cbz	x1, .Lskip_amu_fgt_\@



	msr_s	SYS_HAFGRTR_EL2, xzr



.Lskip_amu_fgt_\@:



.Lskip_fgt_\@:

.endm

arch/arm64/include/asm/esr.h

+44 −44
Original line number Diff line number Diff line
@@ -10,63 +10,63 @@ 
#include <asm/memory.h>

#include <asm/sysreg.h>



#define ESR_ELx_EC_UNKNOWN	(0x00)

#define ESR_ELx_EC_WFx		(0x01)

#define ESR_ELx_EC_UNKNOWN	UL(0x00)

#define ESR_ELx_EC_WFx		UL(0x01)

/* Unallocated EC: 0x02 */

#define ESR_ELx_EC_CP15_32	(0x03)

#define ESR_ELx_EC_CP15_64	(0x04)

#define ESR_ELx_EC_CP14_MR	(0x05)

#define ESR_ELx_EC_CP14_LS	(0x06)

#define ESR_ELx_EC_FP_ASIMD	(0x07)

#define ESR_ELx_EC_CP10_ID	(0x08)	/* EL2 only */

#define ESR_ELx_EC_PAC		(0x09)	/* EL2 and above */

#define ESR_ELx_EC_CP15_32	UL(0x03)

#define ESR_ELx_EC_CP15_64	UL(0x04)

#define ESR_ELx_EC_CP14_MR	UL(0x05)

#define ESR_ELx_EC_CP14_LS	UL(0x06)

#define ESR_ELx_EC_FP_ASIMD	UL(0x07)

#define ESR_ELx_EC_CP10_ID	UL(0x08)	/* EL2 only */

#define ESR_ELx_EC_PAC		UL(0x09)	/* EL2 and above */

/* Unallocated EC: 0x0A - 0x0B */

#define ESR_ELx_EC_CP14_64	(0x0C)

#define ESR_ELx_EC_BTI		(0x0D)

#define ESR_ELx_EC_ILL		(0x0E)

#define ESR_ELx_EC_CP14_64	UL(0x0C)

#define ESR_ELx_EC_BTI		UL(0x0D)

#define ESR_ELx_EC_ILL		UL(0x0E)

/* Unallocated EC: 0x0F - 0x10 */

#define ESR_ELx_EC_SVC32	(0x11)

#define ESR_ELx_EC_HVC32	(0x12)	/* EL2 only */

#define ESR_ELx_EC_SMC32	(0x13)	/* EL2 and above */

#define ESR_ELx_EC_SVC32	UL(0x11)

#define ESR_ELx_EC_HVC32	UL(0x12)	/* EL2 only */

#define ESR_ELx_EC_SMC32	UL(0x13)	/* EL2 and above */

/* Unallocated EC: 0x14 */

#define ESR_ELx_EC_SVC64	(0x15)

#define ESR_ELx_EC_HVC64	(0x16)	/* EL2 and above */

#define ESR_ELx_EC_SMC64	(0x17)	/* EL2 and above */

#define ESR_ELx_EC_SYS64	(0x18)

#define ESR_ELx_EC_SVE		(0x19)

#define ESR_ELx_EC_ERET		(0x1a)	/* EL2 only */

#define ESR_ELx_EC_SVC64	UL(0x15)

#define ESR_ELx_EC_HVC64	UL(0x16)	/* EL2 and above */

#define ESR_ELx_EC_SMC64	UL(0x17)	/* EL2 and above */

#define ESR_ELx_EC_SYS64	UL(0x18)

#define ESR_ELx_EC_SVE		UL(0x19)

#define ESR_ELx_EC_ERET		UL(0x1a)	/* EL2 only */

/* Unallocated EC: 0x1B */

#define ESR_ELx_EC_FPAC		(0x1C)	/* EL1 and above */

#define ESR_ELx_EC_SME		(0x1D)

#define ESR_ELx_EC_FPAC		UL(0x1C)	/* EL1 and above */

#define ESR_ELx_EC_SME		UL(0x1D)

/* Unallocated EC: 0x1E */

#define ESR_ELx_EC_IMP_DEF	(0x1f)	/* EL3 only */

#define ESR_ELx_EC_IABT_LOW	(0x20)

#define ESR_ELx_EC_IABT_CUR	(0x21)

#define ESR_ELx_EC_PC_ALIGN	(0x22)

#define ESR_ELx_EC_IMP_DEF	UL(0x1f)	/* EL3 only */

#define ESR_ELx_EC_IABT_LOW	UL(0x20)

#define ESR_ELx_EC_IABT_CUR	UL(0x21)

#define ESR_ELx_EC_PC_ALIGN	UL(0x22)

/* Unallocated EC: 0x23 */

#define ESR_ELx_EC_DABT_LOW	(0x24)

#define ESR_ELx_EC_DABT_CUR	(0x25)

#define ESR_ELx_EC_SP_ALIGN	(0x26)

#define ESR_ELx_EC_MOPS		(0x27)

#define ESR_ELx_EC_FP_EXC32	(0x28)

#define ESR_ELx_EC_DABT_LOW	UL(0x24)

#define ESR_ELx_EC_DABT_CUR	UL(0x25)

#define ESR_ELx_EC_SP_ALIGN	UL(0x26)

#define ESR_ELx_EC_MOPS		UL(0x27)

#define ESR_ELx_EC_FP_EXC32	UL(0x28)

/* Unallocated EC: 0x29 - 0x2B */

#define ESR_ELx_EC_FP_EXC64	(0x2C)

#define ESR_ELx_EC_FP_EXC64	UL(0x2C)

/* Unallocated EC: 0x2D - 0x2E */

#define ESR_ELx_EC_SERROR	(0x2F)

#define ESR_ELx_EC_BREAKPT_LOW	(0x30)

#define ESR_ELx_EC_BREAKPT_CUR	(0x31)

#define ESR_ELx_EC_SOFTSTP_LOW	(0x32)

#define ESR_ELx_EC_SOFTSTP_CUR	(0x33)

#define ESR_ELx_EC_WATCHPT_LOW	(0x34)

#define ESR_ELx_EC_WATCHPT_CUR	(0x35)

#define ESR_ELx_EC_SERROR	UL(0x2F)

#define ESR_ELx_EC_BREAKPT_LOW	UL(0x30)

#define ESR_ELx_EC_BREAKPT_CUR	UL(0x31)

#define ESR_ELx_EC_SOFTSTP_LOW	UL(0x32)

#define ESR_ELx_EC_SOFTSTP_CUR	UL(0x33)

#define ESR_ELx_EC_WATCHPT_LOW	UL(0x34)

#define ESR_ELx_EC_WATCHPT_CUR	UL(0x35)

/* Unallocated EC: 0x36 - 0x37 */

#define ESR_ELx_EC_BKPT32	(0x38)

#define ESR_ELx_EC_BKPT32	UL(0x38)

/* Unallocated EC: 0x39 */

#define ESR_ELx_EC_VECTOR32	(0x3A)	/* EL2 only */

#define ESR_ELx_EC_VECTOR32	UL(0x3A)	/* EL2 only */

/* Unallocated EC: 0x3B */

#define ESR_ELx_EC_BRK64	(0x3C)

#define ESR_ELx_EC_BRK64	UL(0x3C)

/* Unallocated EC: 0x3D - 0x3F */

#define ESR_ELx_EC_MAX		(0x3F)

#define ESR_ELx_EC_MAX		UL(0x3F)



#define ESR_ELx_EC_SHIFT	(26)

#define ESR_ELx_EC_WIDTH	(6)

arch/arm64/include/asm/fpsimd.h

+0 −2
Original line number Diff line number Diff line
@@ -155,8 +155,6 @@ extern void cpu_enable_sme2(const struct arm64_cpu_capabilities *__unused); 
extern void cpu_enable_fa64(const struct arm64_cpu_capabilities *__unused);

extern void cpu_enable_fpmr(const struct arm64_cpu_capabilities *__unused);



extern u64 read_smcr_features(void);



/*

 * Helpers to translate bit indices in sve_vq_map to VQ values (and

 * vice versa).  This allows find_next_bit() to be used to find the

arch/arm64/include/asm/mmu.h

+0 −1
Original line number Diff line number Diff line
@@ -63,7 +63,6 @@ static inline bool arm64_kernel_unmapped_at_el0(void) 
extern void arm64_memblock_init(void);

extern void paging_init(void);

extern void bootmem_init(void);

extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);

extern void create_mapping_noalloc(phys_addr_t phys, unsigned long virt,

				   phys_addr_t size, pgprot_t prot);

extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,

arch/arm64/include/asm/pgtable-hwdef.h

+0 −1
Original line number Diff line number Diff line
@@ -135,7 +135,6 @@ 
/*

 * Section

 */

#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)

#define PMD_SECT_USER		(_AT(pmdval_t, 1) << 6)		/* AP[1] */

#define PMD_SECT_RDONLY		(_AT(pmdval_t, 1) << 7)		/* AP[2] */

#define PMD_SECT_S		(_AT(pmdval_t, 3) << 8)