Commit f673d59e authored by John Harrison's avatar John Harrison
Browse files

drm/i915: Enable Wa_16019325821 



Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.

Signed-off-by: default avatarJohn Harrison <John.C.Harrison@Intel.com>
Reviewed-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240223205632.1621019-2-John.C.Harrison@Intel.com
parent cec82816

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+11 −8
Original line number Diff line number Diff line
@@ -743,21 +743,23 @@ static u32 *gen12_emit_preempt_busywait(struct i915_request *rq, u32 *cs) 
}



/* Wa_14014475959:dg2 */

#define CCS_SEMAPHORE_PPHWSP_OFFSET	0x540

static u32 ccs_semaphore_offset(struct i915_request *rq)

/* Wa_16019325821 */

#define HOLD_SWITCHOUT_SEMAPHORE_PPHWSP_OFFSET	0x540

static u32 hold_switchout_semaphore_offset(struct i915_request *rq)

{

	return i915_ggtt_offset(rq->context->state) +

		(LRC_PPHWSP_PN * PAGE_SIZE) + CCS_SEMAPHORE_PPHWSP_OFFSET;

		(LRC_PPHWSP_PN * PAGE_SIZE) + HOLD_SWITCHOUT_SEMAPHORE_PPHWSP_OFFSET;

}



/* Wa_14014475959:dg2 */

static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs)

/* Wa_16019325821 */

static u32 *hold_switchout_emit_wa_busywait(struct i915_request *rq, u32 *cs)

{

	int i;



	*cs++ = MI_ATOMIC_INLINE | MI_ATOMIC_GLOBAL_GTT | MI_ATOMIC_CS_STALL |

		MI_ATOMIC_MOVE;

	*cs++ = ccs_semaphore_offset(rq);

	*cs++ = hold_switchout_semaphore_offset(rq);

	*cs++ = 0;

	*cs++ = 1;
@@ -773,7 +775,7 @@ static u32 *ccs_emit_wa_busywait(struct i915_request *rq, u32 *cs) 
		MI_SEMAPHORE_POLL |

		MI_SEMAPHORE_SAD_EQ_SDD;

	*cs++ = 0;

	*cs++ = ccs_semaphore_offset(rq);

	*cs++ = hold_switchout_semaphore_offset(rq);

	*cs++ = 0;



	return cs;
@@ -790,8 +792,9 @@ gen12_emit_fini_breadcrumb_tail(struct i915_request *rq, u32 *cs) 
		cs = gen12_emit_preempt_busywait(rq, cs);



	/* Wa_14014475959:dg2 */

	if (intel_engine_uses_wa_hold_ccs_switchout(rq->engine))

		cs = ccs_emit_wa_busywait(rq, cs);

	/* Wa_16019325821 */

	if (intel_engine_uses_wa_hold_switchout(rq->engine))

		cs = hold_switchout_emit_wa_busywait(rq, cs);



	rq->tail = intel_ring_offset(rq, cs);

	assert_ring_tail_valid(rq->ring, rq->tail);

drivers/gpu/drm/i915/gt/intel_engine_types.h

+4 −3
Original line number Diff line number Diff line
@@ -586,7 +586,7 @@ struct intel_engine_cs { 
#define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)

#define I915_ENGINE_HAS_EU_PRIORITY    BIT(10)

#define I915_ENGINE_FIRST_RENDER_COMPUTE BIT(11)

#define I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT BIT(12)

#define I915_ENGINE_USES_WA_HOLD_SWITCHOUT BIT(12)

	unsigned int flags;



	/*
@@ -696,10 +696,11 @@ intel_engine_has_relative_mmio(const struct intel_engine_cs * const engine) 
}



/* Wa_14014475959:dg2 */

/* Wa_16019325821 */

static inline bool

intel_engine_uses_wa_hold_ccs_switchout(struct intel_engine_cs *engine)

intel_engine_uses_wa_hold_switchout(struct intel_engine_cs *engine)

{

	return engine->flags & I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;

	return engine->flags & I915_ENGINE_USES_WA_HOLD_SWITCHOUT;

}



#endif /* __INTEL_ENGINE_TYPES_H__ */

drivers/gpu/drm/i915/gt/uc/intel_guc.c

+4 −0
Original line number Diff line number Diff line
@@ -294,6 +294,10 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc) 
	    IS_DG2(gt->i915))

		flags |= GUC_WA_HOLD_CCS_SWITCHOUT;



	/* Wa_16019325821 */

	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 71)))

		flags |= GUC_WA_RCS_CCS_SWITCHOUT;



	/*

	 * Wa_14012197797

	 * Wa_22011391025

drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h

+2 −1
Original line number Diff line number Diff line
@@ -96,8 +96,9 @@ 
#define   GUC_WA_GAM_CREDITS		BIT(10)

#define   GUC_WA_DUAL_QUEUE		BIT(11)

#define   GUC_WA_RCS_RESET_BEFORE_RC6	BIT(13)

#define   GUC_WA_CONTEXT_ISOLATION	BIT(15)

#define   GUC_WA_PRE_PARSER		BIT(14)

#define   GUC_WA_CONTEXT_ISOLATION	BIT(15)

#define   GUC_WA_RCS_CCS_SWITCHOUT	BIT(16)

#define   GUC_WA_HOLD_CCS_SWITCHOUT	BIT(17)

#define   GUC_WA_POLLCS			BIT(18)

#define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST	BIT(21)

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

+6 −1
Original line number Diff line number Diff line
@@ -4502,7 +4502,12 @@ static void guc_default_vfuncs(struct intel_engine_cs *engine) 
	if (engine->class == COMPUTE_CLASS)

		if (IS_GFX_GT_IP_STEP(engine->gt, IP_VER(12, 70), STEP_A0, STEP_B0) ||

		    IS_DG2(engine->i915))

			engine->flags |= I915_ENGINE_USES_WA_HOLD_CCS_SWITCHOUT;

			engine->flags |= I915_ENGINE_USES_WA_HOLD_SWITCHOUT;



	/* Wa_16019325821 */

	if ((engine->class == COMPUTE_CLASS || engine->class == RENDER_CLASS) &&

	    IS_GFX_GT_IP_RANGE(engine->gt, IP_VER(12, 70), IP_VER(12, 71)))

		engine->flags |= I915_ENGINE_USES_WA_HOLD_SWITCHOUT;



	/*

	 * TODO: GuC supports timeslicing and semaphores as well, but they're