Commit fef3acf5 authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch kvm-arm64/fgt-masks into kvmarm-master/next 



* kvm-arm64/fgt-masks: (43 commits)
  : .
  : Large rework of the way KVM deals with trap bits in conjunction with
  : the CPU feature registers. It now draws a direct link between which
  : the feature set, the system registers that need to UNDEF to match
  : the configuration and bits that need to behave as RES0 or RES1 in
  : the trap registers that are visible to the guest.
  :
  : Best of all, these definitions are mostly automatically generated
  : from the JSON description published by ARM under a permissive
  : license.
  : .
  KVM: arm64: Handle TSB CSYNC traps
  KVM: arm64: Add FGT descriptors for FEAT_FGT2
  KVM: arm64: Allow sysreg ranges for FGT descriptors
  KVM: arm64: Add context-switch for FEAT_FGT2 registers
  KVM: arm64: Add trap routing for FEAT_FGT2 registers
  KVM: arm64: Add sanitisation for FEAT_FGT2 registers
  KVM: arm64: Add FEAT_FGT2 registers to the VNCR page
  KVM: arm64: Use HCR_EL2 feature map to drive fixed-value bits
  KVM: arm64: Use HCRX_EL2 feature map to drive fixed-value bits
  KVM: arm64: Allow kvm_has_feat() to take variable arguments
  KVM: arm64: Use FGT feature maps to drive RES0 bits
  KVM: arm64: Validate FGT register descriptions against RES0 masks
  KVM: arm64: Switch to table-driven FGU configuration
  KVM: arm64: Handle PSB CSYNC traps
  KVM: arm64: Use KVM-specific HCRX_EL2 RES0 mask
  KVM: arm64: Remove hand-crafted masks for FGT registers
  KVM: arm64: Use computed FGT masks to setup FGT registers
  KVM: arm64: Propagate FGT masks to the nVHE hypervisor
  KVM: arm64: Unconditionally configure fine-grain traps
  KVM: arm64: Use computed masks as sanitisers for FGT registers
  ...

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents 6eb0ed96 98dbe56a

arch/arm64/include/asm/el2_setup.h

+7 −7
Original line number Diff line number Diff line
@@ -213,8 +213,8 @@ 
	cbz	x1, .Lskip_debug_fgt_\@



	/* Disable nVHE traps of TPIDR2 and SMPRI */

	orr	x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK

	orr	x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK

	orr	x0, x0, #HFGRTR_EL2_nSMPRI_EL1_MASK

	orr	x0, x0, #HFGRTR_EL2_nTPIDR2_EL0_MASK



.Lskip_debug_fgt_\@:

	mrs_s	x1, SYS_ID_AA64MMFR3_EL1
@@ -222,8 +222,8 @@ 
	cbz	x1, .Lskip_pie_fgt_\@



	/* Disable trapping of PIR_EL1 / PIRE0_EL1 */

	orr	x0, x0, #HFGxTR_EL2_nPIR_EL1

	orr	x0, x0, #HFGxTR_EL2_nPIRE0_EL1

	orr	x0, x0, #HFGRTR_EL2_nPIR_EL1

	orr	x0, x0, #HFGRTR_EL2_nPIRE0_EL1



.Lskip_pie_fgt_\@:

	mrs_s	x1, SYS_ID_AA64MMFR3_EL1
@@ -231,7 +231,7 @@ 
	cbz	x1, .Lskip_poe_fgt_\@



	/* Disable trapping of POR_EL0 */

	orr	x0, x0, #HFGxTR_EL2_nPOR_EL0

	orr	x0, x0, #HFGRTR_EL2_nPOR_EL0



.Lskip_poe_fgt_\@:

	/* GCS depends on PIE so we don't check it if PIE is absent */
@@ -240,8 +240,8 @@ 
	cbz	x1, .Lset_fgt_\@



	/* Disable traps of access to GCS registers at EL0 and EL1 */

	orr	x0, x0, #HFGxTR_EL2_nGCS_EL1_MASK

	orr	x0, x0, #HFGxTR_EL2_nGCS_EL0_MASK

	orr	x0, x0, #HFGRTR_EL2_nGCS_EL1_MASK

	orr	x0, x0, #HFGRTR_EL2_nGCS_EL0_MASK



.Lset_fgt_\@:

	msr_s	SYS_HFGRTR_EL2, x0

arch/arm64/include/asm/esr.h

+9 −1
Original line number Diff line number Diff line
@@ -20,7 +20,8 @@ 
#define ESR_ELx_EC_FP_ASIMD	UL(0x07)

#define ESR_ELx_EC_CP10_ID	UL(0x08)	/* EL2 only */

#define ESR_ELx_EC_PAC		UL(0x09)	/* EL2 and above */

/* Unallocated EC: 0x0A - 0x0B */

#define ESR_ELx_EC_OTHER	UL(0x0A)

/* Unallocated EC: 0x0B */

#define ESR_ELx_EC_CP14_64	UL(0x0C)

#define ESR_ELx_EC_BTI		UL(0x0D)

#define ESR_ELx_EC_ILL		UL(0x0E)
@@ -181,6 +182,13 @@ 
#define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)

#define ESR_ELx_xVC_IMM_MASK	((UL(1) << 16) - 1)



/* ISS definitions for LD64B/ST64B/{T,P}SBCSYNC instructions */

#define ESR_ELx_ISS_OTHER_ST64BV	(0)

#define ESR_ELx_ISS_OTHER_ST64BV0	(1)

#define ESR_ELx_ISS_OTHER_LDST64B	(2)

#define ESR_ELx_ISS_OTHER_TSBCSYNC	(3)

#define ESR_ELx_ISS_OTHER_PSBCSYNC	(4)



#define DISR_EL1_IDS		(UL(1) << 24)

/*

 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean

arch/arm64/include/asm/kvm_arm.h

+76 −110
Original line number Diff line number Diff line
@@ -12,67 +12,70 @@ 
#include <asm/sysreg.h>

#include <asm/types.h>



/* Hyp Configuration Register (HCR) bits */



#define HCR_TID5	(UL(1) << 58)

#define HCR_DCT		(UL(1) << 57)

#define HCR_ATA_SHIFT	56

#define HCR_ATA		(UL(1) << HCR_ATA_SHIFT)

#define HCR_TTLBOS	(UL(1) << 55)

#define HCR_TTLBIS	(UL(1) << 54)

#define HCR_ENSCXT	(UL(1) << 53)

#define HCR_TOCU	(UL(1) << 52)

#define HCR_AMVOFFEN	(UL(1) << 51)

#define HCR_TICAB	(UL(1) << 50)

#define HCR_TID4	(UL(1) << 49)

#define HCR_FIEN	(UL(1) << 47)

#define HCR_FWB		(UL(1) << 46)

#define HCR_NV2		(UL(1) << 45)

#define HCR_AT		(UL(1) << 44)

#define HCR_NV1		(UL(1) << 43)

#define HCR_NV		(UL(1) << 42)

#define HCR_API		(UL(1) << 41)

#define HCR_APK		(UL(1) << 40)

#define HCR_TEA		(UL(1) << 37)

#define HCR_TERR	(UL(1) << 36)

#define HCR_TLOR	(UL(1) << 35)

#define HCR_E2H		(UL(1) << 34)

#define HCR_ID		(UL(1) << 33)

#define HCR_CD		(UL(1) << 32)

#define HCR_RW_SHIFT	31

#define HCR_RW		(UL(1) << HCR_RW_SHIFT)

#define HCR_TRVM	(UL(1) << 30)

#define HCR_HCD		(UL(1) << 29)

#define HCR_TDZ		(UL(1) << 28)

#define HCR_TGE		(UL(1) << 27)

#define HCR_TVM		(UL(1) << 26)

#define HCR_TTLB	(UL(1) << 25)

#define HCR_TPU		(UL(1) << 24)

#define HCR_TPC		(UL(1) << 23) /* HCR_TPCP if FEAT_DPB */

#define HCR_TSW		(UL(1) << 22)

#define HCR_TACR	(UL(1) << 21)

#define HCR_TIDCP	(UL(1) << 20)

#define HCR_TSC		(UL(1) << 19)

#define HCR_TID3	(UL(1) << 18)

#define HCR_TID2	(UL(1) << 17)

#define HCR_TID1	(UL(1) << 16)

#define HCR_TID0	(UL(1) << 15)

#define HCR_TWE		(UL(1) << 14)

#define HCR_TWI		(UL(1) << 13)

#define HCR_DC		(UL(1) << 12)

#define HCR_BSU		(3 << 10)

#define HCR_BSU_IS	(UL(1) << 10)

#define HCR_FB		(UL(1) << 9)

#define HCR_VSE		(UL(1) << 8)

#define HCR_VI		(UL(1) << 7)

#define HCR_VF		(UL(1) << 6)

#define HCR_AMO		(UL(1) << 5)

#define HCR_IMO		(UL(1) << 4)

#define HCR_FMO		(UL(1) << 3)

#define HCR_PTW		(UL(1) << 2)

#define HCR_SWIO	(UL(1) << 1)

#define HCR_VM		(UL(1) << 0)

#define HCR_RES0	((UL(1) << 48) | (UL(1) << 39))

/*

 * Because I'm terribly lazy and that repainting the whole of the KVM

 * code with the proper names is a pain, use a helper to map the names

 * inherited from AArch32 with the new fancy nomenclature. One day...

 */

#define	__HCR(x)	HCR_EL2_##x



#define HCR_TID5	__HCR(TID5)

#define HCR_DCT		__HCR(DCT)

#define HCR_ATA_SHIFT	__HCR(ATA_SHIFT)

#define HCR_ATA		__HCR(ATA)

#define HCR_TTLBOS	__HCR(TTLBOS)

#define HCR_TTLBIS	__HCR(TTLBIS)

#define HCR_ENSCXT	__HCR(EnSCXT)

#define HCR_TOCU	__HCR(TOCU)

#define HCR_AMVOFFEN	__HCR(AMVOFFEN)

#define HCR_TICAB	__HCR(TICAB)

#define HCR_TID4	__HCR(TID4)

#define HCR_FIEN	__HCR(FIEN)

#define HCR_FWB		__HCR(FWB)

#define HCR_NV2		__HCR(NV2)

#define HCR_AT		__HCR(AT)

#define HCR_NV1		__HCR(NV1)

#define HCR_NV		__HCR(NV)

#define HCR_API		__HCR(API)

#define HCR_APK		__HCR(APK)

#define HCR_TEA		__HCR(TEA)

#define HCR_TERR	__HCR(TERR)

#define HCR_TLOR	__HCR(TLOR)

#define HCR_E2H		__HCR(E2H)

#define HCR_ID		__HCR(ID)

#define HCR_CD		__HCR(CD)

#define HCR_RW		__HCR(RW)

#define HCR_TRVM	__HCR(TRVM)

#define HCR_HCD		__HCR(HCD)

#define HCR_TDZ		__HCR(TDZ)

#define HCR_TGE		__HCR(TGE)

#define HCR_TVM		__HCR(TVM)

#define HCR_TTLB	__HCR(TTLB)

#define HCR_TPU		__HCR(TPU)

#define HCR_TPC		__HCR(TPCP)

#define HCR_TSW		__HCR(TSW)

#define HCR_TACR	__HCR(TACR)

#define HCR_TIDCP	__HCR(TIDCP)

#define HCR_TSC		__HCR(TSC)

#define HCR_TID3	__HCR(TID3)

#define HCR_TID2	__HCR(TID2)

#define HCR_TID1	__HCR(TID1)

#define HCR_TID0	__HCR(TID0)

#define HCR_TWE		__HCR(TWE)

#define HCR_TWI		__HCR(TWI)

#define HCR_DC		__HCR(DC)

#define HCR_BSU		__HCR(BSU)

#define HCR_BSU_IS	__HCR(BSU_IS)

#define HCR_FB		__HCR(FB)

#define HCR_VSE		__HCR(VSE)

#define HCR_VI		__HCR(VI)

#define HCR_VF		__HCR(VF)

#define HCR_AMO		__HCR(AMO)

#define HCR_IMO		__HCR(IMO)

#define HCR_FMO		__HCR(FMO)

#define HCR_PTW		__HCR(PTW)

#define HCR_SWIO	__HCR(SWIO)

#define HCR_VM		__HCR(VM)



/*

 * The bits we set in HCR:
@@ -313,56 +316,19 @@ 
				 GENMASK(15, 0))



/*

 * FGT register definitions

 *

 * RES0 and polarity masks as of DDI0487J.a, to be updated as needed.

 * We're not using the generated masks as they are usually ahead of

 * the published ARM ARM, which we use as a reference.

 *

 * Once we get to a point where the two describe the same thing, we'll

 * merge the definitions. One day.

 */

#define __HFGRTR_EL2_RES0	HFGxTR_EL2_RES0

#define __HFGRTR_EL2_MASK	GENMASK(49, 0)

#define __HFGRTR_EL2_nMASK	~(__HFGRTR_EL2_RES0 | __HFGRTR_EL2_MASK)



/*

 * The HFGWTR bits are a subset of HFGRTR bits. To ensure we don't miss any

 * future additions, define __HFGWTR* macros relative to __HFGRTR* ones.

 * Polarity masks for HCRX_EL2, limited to the bits that we know about

 * at this point in time. It doesn't mean that we actually *handle*

 * them, but that at least those that are not advertised to a guest

 * will be RES0 for that guest.

 */

#define __HFGRTR_ONLY_MASK	(BIT(46) | BIT(42) | BIT(40) | BIT(28) | \

				 GENMASK(26, 25) | BIT(21) | BIT(18) | \

				 GENMASK(15, 14) | GENMASK(10, 9) | BIT(2))

#define __HFGWTR_EL2_RES0	(__HFGRTR_EL2_RES0 | __HFGRTR_ONLY_MASK)

#define __HFGWTR_EL2_MASK	(__HFGRTR_EL2_MASK & ~__HFGRTR_ONLY_MASK)

#define __HFGWTR_EL2_nMASK	~(__HFGWTR_EL2_RES0 | __HFGWTR_EL2_MASK)



#define __HFGITR_EL2_RES0	HFGITR_EL2_RES0

#define __HFGITR_EL2_MASK	(BIT(62) | BIT(60) | GENMASK(54, 0))

#define __HFGITR_EL2_nMASK	~(__HFGITR_EL2_RES0 | __HFGITR_EL2_MASK)



#define __HDFGRTR_EL2_RES0	HDFGRTR_EL2_RES0

#define __HDFGRTR_EL2_MASK	(BIT(63) | GENMASK(58, 50) | GENMASK(48, 43) | \

				 GENMASK(41, 40) | GENMASK(37, 22) | \

				 GENMASK(19, 9) | GENMASK(7, 0))

#define __HDFGRTR_EL2_nMASK	~(__HDFGRTR_EL2_RES0 | __HDFGRTR_EL2_MASK)



#define __HDFGWTR_EL2_RES0	HDFGWTR_EL2_RES0

#define __HDFGWTR_EL2_MASK	(GENMASK(57, 52) | GENMASK(50, 48) | \

				 GENMASK(46, 44) | GENMASK(42, 41) | \

				 GENMASK(37, 35) | GENMASK(33, 31) | \

				 GENMASK(29, 23) | GENMASK(21, 10) | \

				 GENMASK(8, 7) | GENMASK(5, 0))

#define __HDFGWTR_EL2_nMASK	~(__HDFGWTR_EL2_RES0 | __HDFGWTR_EL2_MASK)



#define __HAFGRTR_EL2_RES0	HAFGRTR_EL2_RES0

#define __HAFGRTR_EL2_MASK	(GENMASK(49, 17) | GENMASK(4, 0))

#define __HAFGRTR_EL2_nMASK	~(__HAFGRTR_EL2_RES0 | __HAFGRTR_EL2_MASK)



/* Similar definitions for HCRX_EL2 */

#define __HCRX_EL2_RES0         HCRX_EL2_RES0

#define __HCRX_EL2_MASK		(BIT(6))

#define __HCRX_EL2_nMASK	~(__HCRX_EL2_RES0 | __HCRX_EL2_MASK)

#define __HCRX_EL2_MASK		(BIT_ULL(6))

#define __HCRX_EL2_nMASK	(GENMASK_ULL(24, 14) | \

				 GENMASK_ULL(11, 7)  | \

				 GENMASK_ULL(5, 0))

#define __HCRX_EL2_RES0		~(__HCRX_EL2_nMASK | __HCRX_EL2_MASK)

#define __HCRX_EL2_RES1		~(__HCRX_EL2_nMASK | \

				  __HCRX_EL2_MASK  | \

				  __HCRX_EL2_RES0)



/* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */

#define HPFAR_MASK	(~UL(0xf))

arch/arm64/include/asm/kvm_host.h

+54 −3
Original line number Diff line number Diff line
@@ -273,11 +273,17 @@ struct kvm_sysreg_masks; 


enum fgt_group_id {

	__NO_FGT_GROUP__,

	HFGxTR_GROUP,

	HFGRTR_GROUP,

	HFGWTR_GROUP = HFGRTR_GROUP,

	HDFGRTR_GROUP,

	HDFGWTR_GROUP = HDFGRTR_GROUP,

	HFGITR_GROUP,

	HAFGRTR_GROUP,

	HFGRTR2_GROUP,

	HFGWTR2_GROUP = HFGRTR2_GROUP,

	HDFGRTR2_GROUP,

	HDFGWTR2_GROUP = HDFGRTR2_GROUP,

	HFGITR2_GROUP,



	/* Must be last */

	__NR_FGT_GROUP_IDS__
@@ -561,6 +567,11 @@ enum vcpu_sysreg { 
	VNCR(HDFGRTR_EL2),

	VNCR(HDFGWTR_EL2),

	VNCR(HAFGRTR_EL2),

	VNCR(HFGRTR2_EL2),

	VNCR(HFGWTR2_EL2),

	VNCR(HFGITR2_EL2),

	VNCR(HDFGRTR2_EL2),

	VNCR(HDFGWTR2_EL2),



	VNCR(CNTVOFF_EL2),

	VNCR(CNTV_CVAL_EL0),
@@ -606,6 +617,37 @@ struct kvm_sysreg_masks { 
	} mask[NR_SYS_REGS - __SANITISED_REG_START__];

};



struct fgt_masks {

	const char	*str;

	u64		mask;

	u64		nmask;

	u64		res0;

};



extern struct fgt_masks hfgrtr_masks;

extern struct fgt_masks hfgwtr_masks;

extern struct fgt_masks hfgitr_masks;

extern struct fgt_masks hdfgrtr_masks;

extern struct fgt_masks hdfgwtr_masks;

extern struct fgt_masks hafgrtr_masks;

extern struct fgt_masks hfgrtr2_masks;

extern struct fgt_masks hfgwtr2_masks;

extern struct fgt_masks hfgitr2_masks;

extern struct fgt_masks hdfgrtr2_masks;

extern struct fgt_masks hdfgwtr2_masks;



extern struct fgt_masks kvm_nvhe_sym(hfgrtr_masks);

extern struct fgt_masks kvm_nvhe_sym(hfgwtr_masks);

extern struct fgt_masks kvm_nvhe_sym(hfgitr_masks);

extern struct fgt_masks kvm_nvhe_sym(hdfgrtr_masks);

extern struct fgt_masks kvm_nvhe_sym(hdfgwtr_masks);

extern struct fgt_masks kvm_nvhe_sym(hafgrtr_masks);

extern struct fgt_masks kvm_nvhe_sym(hfgrtr2_masks);

extern struct fgt_masks kvm_nvhe_sym(hfgwtr2_masks);

extern struct fgt_masks kvm_nvhe_sym(hfgitr2_masks);

extern struct fgt_masks kvm_nvhe_sym(hdfgrtr2_masks);

extern struct fgt_masks kvm_nvhe_sym(hdfgwtr2_masks);



struct kvm_cpu_context {

	struct user_pt_regs regs;	/* sp = sp_el0 */
@@ -1552,12 +1594,16 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val); 
	 kvm_cmp_feat_signed(kvm, id, fld, op, limit) :			\

	 kvm_cmp_feat_unsigned(kvm, id, fld, op, limit))



#define kvm_has_feat(kvm, id, fld, limit)				\

#define __kvm_has_feat(kvm, id, fld, limit)				\

	kvm_cmp_feat(kvm, id, fld, >=, limit)



#define kvm_has_feat_enum(kvm, id, fld, val)				\

#define kvm_has_feat(kvm, ...) __kvm_has_feat(kvm, __VA_ARGS__)



#define __kvm_has_feat_enum(kvm, id, fld, val)				\

	kvm_cmp_feat_unsigned(kvm, id, fld, ==, val)



#define kvm_has_feat_enum(kvm, ...) __kvm_has_feat_enum(kvm, __VA_ARGS__)



#define kvm_has_feat_range(kvm, id, fld, min, max)			\

	(kvm_cmp_feat(kvm, id, fld, >=, min) &&				\

	kvm_cmp_feat(kvm, id, fld, <=, max))
@@ -1595,4 +1641,9 @@ static inline bool kvm_arch_has_irq_bypass(void) 
	return true;

}



void compute_fgu(struct kvm *kvm, enum fgt_group_id fgt);

void get_reg_fixed_bits(struct kvm *kvm, enum vcpu_sysreg reg, u64 *res0, u64 *res1);

void check_feature_map(void);





#endif /* __ARM64_KVM_HOST_H__ */

arch/arm64/include/asm/sysreg.h

+14 −12
Original line number Diff line number Diff line
@@ -117,6 +117,7 @@ 


#define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)



/* Data cache zero operations */

#define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)

#define SYS_DC_IGSW			sys_insn(1, 0, 7, 6, 4)

#define SYS_DC_IGDSW			sys_insn(1, 0, 7, 6, 6)
@@ -153,11 +154,13 @@ 
#define SYS_DC_CIGVAC			sys_insn(1, 3, 7, 14, 3)

#define SYS_DC_CIGDVAC			sys_insn(1, 3, 7, 14, 5)



/* Data cache zero operations */

#define SYS_DC_ZVA			sys_insn(1, 3, 7, 4, 1)

#define SYS_DC_GVA			sys_insn(1, 3, 7, 4, 3)

#define SYS_DC_GZVA			sys_insn(1, 3, 7, 4, 4)



#define SYS_DC_CIVAPS			sys_insn(1, 0, 7, 15, 1)

#define SYS_DC_CIGDVAPS			sys_insn(1, 0, 7, 15, 5)



/*

 * Automatically generated definitions for system registers, the

 * manual encodings below are in the process of being converted to
@@ -497,12 +500,22 @@ 


#define __PMEV_op2(n)			((n) & 0x7)

#define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))

#define SYS_PMEVCNTSVRn_EL1(n)		sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n))

#define SYS_PMEVCNTRn_EL0(n)		sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))

#define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))

#define SYS_PMEVTYPERn_EL0(n)		sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))



#define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)



#define	SYS_SPMCGCRn_EL1(n)		sys_reg(2, 0, 9, 13, ((n) & 1))



#define __SPMEV_op2(n)			((n) & 0x7)

#define __SPMEV_crm(p, n)		((((p) & 7) << 1) | (((n) >> 3) & 1))

#define SYS_SPMEVCNTRn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n))

#define	SYS_SPMEVFILT2Rn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n))

#define	SYS_SPMEVFILTRn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n))

#define	SYS_SPMEVTYPERn_EL0(n)		sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n))



#define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)

#define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
@@ -522,7 +535,6 @@ 
#define SYS_VTCR_EL2			sys_reg(3, 4, 2, 1, 2)



#define SYS_VNCR_EL2			sys_reg(3, 4, 2, 2, 0)

#define SYS_HAFGRTR_EL2			sys_reg(3, 4, 3, 1, 6)

#define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)

#define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)

#define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
@@ -608,28 +620,18 @@ 


/* VHE encodings for architectural EL0/1 system registers */

#define SYS_BRBCR_EL12			sys_reg(2, 5, 9, 0, 0)

#define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)

#define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)

#define SYS_SCTLR2_EL12			sys_reg(3, 5, 1, 0, 3)

#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)

#define SYS_TRFCR_EL12			sys_reg(3, 5, 1, 2, 1)

#define SYS_SMCR_EL12			sys_reg(3, 5, 1, 2, 6)

#define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)

#define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)

#define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)

#define SYS_TCR2_EL12			sys_reg(3, 5, 2, 0, 3)

#define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)

#define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)

#define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)

#define SYS_AFSR1_EL12			sys_reg(3, 5, 5, 1, 1)

#define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)

#define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)

#define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)

#define SYS_PMSCR_EL12			sys_reg(3, 5, 9, 9, 0)

#define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)

#define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)

#define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)

#define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)

#define SYS_SCXTNUM_EL12		sys_reg(3, 5, 13, 0, 7)

#define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)

#define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)