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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

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Pull clk updates from Stephen Boyd:
 "Not much changed in the clk framework this time except the clk.h
  consumer API moved the context saving APIs around to fix a build error
  in certain configurations.

  There was a change to the core framework for CLK_OPS_PARENT_ENABLE
  behavior during registration, but it wrecked existing drivers that
  didn't expect things to be turned off during clk registration so it
  got reverted.

  This cycle is really a large collection of new clk drivers, primarily
  for Qualcomm SoCs but also for Amlogic, SpacemiT, Google, and Aspeed.
  Another big change in here is support for automatic hardware clock
  gating on Samsung SoCs where the clks turn on and off when needed.
  Ideally more vendors move to this method for better power savings. The
  highlights are in the updates section below.

  Beyond all the new drivers we have a bunch of cleanups like converting
  drivers from divider_round_rate() to divider_determine_rate() and
  using scoped for each OF child loops. Otherwise it's the usual data
  fixes and plugging reference leaks, etc. that's all pretty ordinary
  but not critical enough to fix until the next release.

  New Drivers:
   - Qualcomm Kaanapali global, tcsr, rpmh, display, gpu, camera, and
     video clk controllers
   - Qualcomm SM8750 camera clk controllers
   - Qualcomm MSM8940 and SDM439 global clk controllers
   - Google GS101 Display Process Unit (DPU) clk controllers
   - SpacemiT K3 clk controllers
   - Amlogic t7 clk controllers
   - Aspeed AST2700 clk controllers

  Updates:
   - Convert clock dividers from round_rate() to determine_rate()
   - Fix sparse warnings, kernel-doc warnings, and plug leaked OF refs
   - Automatic hardware clk gating on Google GS101 SoCs
   - Amlogic s4 video clks
   - CAN-FD clks and resets on Renesas RZ/T2H, RZ/N2H, RZ/V2H, and
     RZ/V2N
   - Expanded Serial Peripheral Interface (xSPI) clocks and resets on
     Renesas RZ/T21H and RZ/N2H
   - DMAC, interrupt controller (ICU), SPI, and thermal (TSU) clocks and
     resets on Renesas RZ/V2N
   - More serial (RSCI) clocks and resets on Renesas RZ/V2H and RZ/V2N
   - CPU frequency scaling on T-HEAD TH1520"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (165 commits)
  clk: aspeed: Add reset for HACE/VIDEO
  dt-bindings: clock: aspeed: Add VIDEO reset definition
  clk: aspeed: add AST2700 clock driver
  MAINTAINERS: Add entry for ASPEED clock drivers.
  clk: aspeed: Move the existing ASPEED clk drivers into aspeed subdirectory.
  Revert "clk: Respect CLK_OPS_PARENT_ENABLE during recalc"
  clk: Disable KUNIT_UML_PCI
  dt-bindings: clk: rs9: Fix DIF pattern match
  clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
  clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
  clk: qcom: sm8750: Constify 'qcom_cc_desc' in SM8750 camcc
  clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: mediatek: Fix error handling in runtime PM setup
  clk: mediatek: don't select clk-mt8192 for all ARM64 builds
  clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks
  clk: mediatek: Refactor pllfh registration to pass device
  clk: mediatek: Pass device to clk_hw_register for PLLs
  clk: mediatek: Refactor pll registration to pass device
  clk: Respect CLK_OPS_PARENT_ENABLE during recalc
  ...
This commit is contained in:
Linus Torvalds
2026-02-15 08:18:57 -08:00
parent ca4ee40bf1 5921ae27ea
commit 13c916af3a
189 changed files with 23418 additions and 944 deletions
Download Patch File Download Diff File Expand all files Collapse all files

116
Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml Normal file
View File

@@ -0,0 +1,116 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,t7-peripherals-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic T7 Peripherals Clock Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
- Jian Hu <jian.hu@amlogic.com>
properties:
compatible:
const: amlogic,t7-peripherals-clkc
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
minItems: 14
items:
- description: input oscillator
- description: input sys clk
- description: input fixed pll
- description: input fclk div 2
- description: input fclk div 2p5
- description: input fclk div 3
- description: input fclk div 4
- description: input fclk div 5
- description: input fclk div 7
- description: input hifi pll
- description: input gp0 pll
- description: input gp1 pll
- description: input mpll1
- description: input mpll2
- description: external input rmii oscillator (optional)
- description: input video pll0 (optional)
- description: external pad input for rtc (optional)
clock-names:
minItems: 14
items:
- const: xtal
- const: sys
- const: fix
- const: fdiv2
- const: fdiv2p5
- const: fdiv3
- const: fdiv4
- const: fdiv5
- const: fdiv7
- const: hifi
- const: gp0
- const: gp1
- const: mpll1
- const: mpll2
- const: ext_rmii
- const: vid_pll0
- const: ext_rtc
required:
- compatible
- '#clock-cells'
- reg
- clocks
- clock-names
additionalProperties: false
examples:
- |
apb {
#address-cells = <2>;
#size-cells = <2>;
clkc_periphs:clock-controller@0 {
compatible = "amlogic,t7-peripherals-clkc";
reg = <0 0x0 0 0x1c8>;
#clock-cells = <1>;
clocks = <&xtal>,
<&scmi_clk 13>,
<&scmi_clk 16>,
<&scmi_clk 18>,
<&scmi_clk 20>,
<&scmi_clk 22>,
<&scmi_clk 24>,
<&scmi_clk 26>,
<&scmi_clk 28>,
<&hifi 1>,
<&gp0 1>,
<&gp1 1>,
<&mpll 4>,
<&mpll 6>;
clock-names = "xtal",
"sys",
"fix",
"fdiv2",
"fdiv2p5",
"fdiv3",
"fdiv4",
"fdiv5",
"fdiv7",
"hifi",
"gp0",
"gp1",
"mpll1",
"mpll2";
};
};

114
Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml Normal file
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@@ -0,0 +1,114 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2024-2025 Amlogic, Inc. All rights reserved
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/amlogic,t7-pll-clkc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic T7 PLL Clock Control Controller
maintainers:
- Neil Armstrong <neil.armstrong@linaro.org>
- Jerome Brunet <jbrunet@baylibre.com>
- Jian Hu <jian.hu@amlogic.com>
- Xianwei Zhao <xianwei.zhao@amlogic.com>
properties:
compatible:
enum:
- amlogic,t7-gp0-pll
- amlogic,t7-gp1-pll
- amlogic,t7-hifi-pll
- amlogic,t7-pcie-pll
- amlogic,t7-mpll
- amlogic,t7-hdmi-pll
- amlogic,t7-mclk-pll
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
items:
- description: mclk pll input oscillator gate
- description: oscillator input clock source for mclk_sel_0
- description: fixed input clock source for mclk_sel_0
minItems: 1
clock-names:
items:
- const: in0
- const: in1
- const: in2
minItems: 1
required:
- compatible
- '#clock-cells'
- reg
- clocks
- clock-names
allOf:
- if:
properties:
compatible:
contains:
const: amlogic,t7-mclk-pll
then:
properties:
clocks:
minItems: 3
clock-names:
minItems: 3
- if:
properties:
compatible:
contains:
enum:
- amlogic,t7-gp0-pll
- amlogic,t7-gp1--pll
- amlogic,t7-hifi-pll
- amlogic,t7-pcie-pll
- amlogic,t7-mpll
- amlogic,t7-hdmi-pll
then:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
additionalProperties: false
examples:
- |
apb {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@8080 {
compatible = "amlogic,t7-gp0-pll";
reg = <0 0x8080 0 0x20>;
clocks = <&scmi_clk 2>;
clock-names = "in0";
#clock-cells = <1>;
};
clock-controller@8300 {
compatible = "amlogic,t7-mclk-pll";
reg = <0 0x8300 0 0x18>;
clocks = <&scmi_clk 2>,
<&xtal>,
<&scmi_clk 31>;
clock-names = "in0", "in1", "in2";
#clock-cells = <1>;
};
};

19
Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
View File

@@ -53,6 +53,11 @@ properties:
reg:
maxItems: 1
samsung,sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to system registers interface.
required:
- compatible
- "#clock-cells"
@@ -185,6 +190,18 @@ allOf:
- const: bus
- const: ip
- if:
properties:
compatible:
contains:
const: google,gs101-cmu-top
then:
properties:
samsung,sysreg: false
else:
required:
- samsung,sysreg
additionalProperties: false
examples:
@@ -194,7 +211,7 @@ examples:
cmu_top: clock-controller@1e080000 {
compatible = "google,gs101-cmu-top";
reg = <0x1e080000 0x8000>;
reg = <0x1e080000 0x10000>;
#clock-cells = <1>;
clocks = <&ext_24_5m>;
clock-names = "oscclk";

10
Documentation/devicetree/bindings/clock/mediatek,mt7622-pciesys.yaml
View File

@@ -14,11 +14,9 @@ maintainers:
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt7622-pciesys
- const: syscon
- const: mediatek,mt7629-pciesys
enum:
- mediatek,mt7622-pciesys
- mediatek,mt7629-pciesys
reg:
maxItems: 1
@@ -40,7 +38,7 @@ additionalProperties: false
examples:
- |
clock-controller@1a100800 {
compatible = "mediatek,mt7622-pciesys", "syscon";
compatible = "mediatek,mt7622-pciesys";
reg = <0x1a100800 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;

6
Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml
View File

@@ -17,7 +17,11 @@ description: |
properties:
compatible:
const: microchip,mpfs-ccc
oneOf:
- items:
- const: microchip,pic64gx-ccc
- const: microchip,mpfs-ccc
- const: microchip,mpfs-ccc
reg:
items:

16
Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
View File

@@ -19,7 +19,11 @@ description: |
properties:
compatible:
const: microchip,mpfs-clkcfg
oneOf:
- items:
- const: microchip,pic64gx-clkcfg
- const: microchip,mpfs-clkcfg
- const: microchip,mpfs-clkcfg
reg:
oneOf:
@@ -69,6 +73,16 @@ required:
- clocks
- '#clock-cells'
if:
properties:
compatible:
contains:
const: microchip,pic64gx-clkcfg
then:
properties:
reg:
maxItems: 1
additionalProperties: false
examples:

6
Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
View File

@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8953.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on MSM8953
title: Qualcomm Global Clock & Reset Controller on MSM8937, MSM8940, MSM8953 and SDM439
maintainers:
- Adam Skladowski <a_skl39@protonmail.com>
@@ -13,7 +13,7 @@ maintainers:
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8937 or MSM8953.
domains on MSM8937, MSM8940, MSM8953 or SDM439.
See also::
include/dt-bindings/clock/qcom,gcc-msm8917.h
@@ -23,7 +23,9 @@ properties:
compatible:
enum:
- qcom,gcc-msm8937
- qcom,gcc-msm8940
- qcom,gcc-msm8953
- qcom,gcc-sdm439
clocks:
items:

63
Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml Normal file
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@@ -0,0 +1,63 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,kaanapali-gxclkctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics power domain Controller on Kaanapali
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and
Power domains (GDSC). This module provides the power domains control
of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem.
See also:
include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h
properties:
compatible:
enum:
- qcom,kaanapali-gxclkctl
power-domains:
description:
Power domains required for the clock controller to operate
items:
- description: GFX power domain
- description: GMXC power domain
- description: GPUCC(CX) power domain
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- power-domains
- '#power-domain-cells'
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/power/qcom,rpmhpd.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@3d64000 {
compatible = "qcom,kaanapali-gxclkctl";
reg = <0x0 0x03d64000 0x0 0x6000>;
power-domains = <&rpmhpd RPMHPD_GFX>,
<&rpmhpd RPMHPD_GMXC>,
<&gpucc 0>;
#power-domain-cells = <1>;
};
};
...

11
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
View File

@@ -9,23 +9,32 @@ title: Qualcomm Camera Clock & Reset Controller on SM8450
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
- Jagadeesh Kona <quic_jkona@quicinc.com>
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm camera clock control module provides the clocks, resets and power
domains on SM8450.
See also:
include/dt-bindings/clock/qcom,kaanapali-camcc.h
include/dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sm8650-camcc.h
include/dt-bindings/clock/qcom,sm8750-cambistmclkcc.h
include/dt-bindings/clock/qcom,sm8750-camcc.h
properties:
compatible:
enum:
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,sm8450-camcc
- qcom,sm8475-camcc
- qcom,sm8550-camcc
- qcom,sm8650-camcc
- qcom,sm8750-cambistmclkcc
- qcom,sm8750-camcc
clocks:
items:
@@ -63,6 +72,8 @@ allOf:
compatible:
contains:
enum:
- qcom,kaanapali-cambistmclkcc
- qcom,kaanapali-camcc
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc

2
Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
View File

@@ -14,6 +14,7 @@ description: |
domains on Qualcomm SoCs.
See also::
include/dt-bindings/clock/qcom,kaanapali-gpucc.h
include/dt-bindings/clock/qcom,milos-gpucc.h
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
include/dt-bindings/clock/qcom,sm4450-gpucc.h
@@ -26,6 +27,7 @@ description: |
properties:
compatible:
enum:
- qcom,kaanapali-gpucc
- qcom,milos-gpucc
- qcom,sar2130p-gpucc
- qcom,sm4450-gpucc

3
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View File

@@ -15,6 +15,7 @@ description: |
domains on SM8450.
See also:
include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
@@ -22,6 +23,7 @@ description: |
properties:
compatible:
enum:
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
- qcom,sm8550-videocc
@@ -61,6 +63,7 @@ allOf:
compatible:
contains:
enum:
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8750-videocc

2
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
View File

@@ -15,6 +15,7 @@ description: |
domains on SM8550, SM8650, SM8750 and few other platforms.
See also:
- include/dt-bindings/clock/qcom,kaanapali-dispcc.h
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,sm8750-dispcc.h
@@ -23,6 +24,7 @@ description: |
properties:
compatible:
enum:
- qcom,kaanapali-dispcc
- qcom,sar2130p-dispcc
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc

11
Documentation/devicetree/bindings/clock/renesas,9series.yaml
View File

@@ -62,7 +62,7 @@ properties:
description: Output clock down spread in pcm (1/1000 of percent)
patternProperties:
"^DIF[0-19]$":
"^DIF1?[0-9]$":
type: object
description:
Description of one of the outputs (DIF0..DIF19).
@@ -107,6 +107,15 @@ examples:
DIF0 {
renesas,slew-rate = <3000000>;
};
/* Not present on 9FGV0241, used for DT validation only */
DIF2 {
renesas,slew-rate = <2000000>;
};
DIF19 {
renesas,slew-rate = <3000000>;
};
};
};

19
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
View File

@@ -40,6 +40,7 @@ properties:
- samsung,exynosautov920-cmu-hsi2
- samsung,exynosautov920-cmu-m2m
- samsung,exynosautov920-cmu-mfc
- samsung,exynosautov920-cmu-mfd
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
@@ -268,6 +269,24 @@ allOf:
- const: mfc
- const: wfd
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-mfd
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_MFD NOC clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
required:
- compatible
- "#clock-cells"

9
Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml
View File

@@ -4,14 +4,16 @@
$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT K1 PLL
title: SpacemiT K1/K3 PLL
maintainers:
- Haylen Chu <heylenay@4d2.org>
properties:
compatible:
const: spacemit,k1-pll
enum:
- spacemit,k1-pll
- spacemit,k3-pll
reg:
maxItems: 1
@@ -28,7 +30,8 @@ properties:
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K1 SoC, check <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K3 SoC, check <dt-bindings/clock/spacemit,k3-clocks.h> for valid indices.
required:
- compatible

2
Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
View File

@@ -15,6 +15,7 @@ properties:
- items:
- enum:
- google,gs101-apm-sysreg
- google,gs101-dpu-sysreg
- google,gs101-hsi0-sysreg
- google,gs101-hsi2-sysreg
- google,gs101-misc-sysreg
@@ -92,6 +93,7 @@ allOf:
compatible:
contains:
enum:
- google,gs101-dpu-sysreg
- google,gs101-hsi0-sysreg
- google,gs101-hsi2-sysreg
- google,gs101-misc-sysreg

14
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
View File

@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SpacemiT K1 SoC System Controller
title: SpacemiT K1/K3 SoC System Controller
maintainers:
- Haylen Chu <heylenay@4d2.org>
@@ -22,6 +22,10 @@ properties:
- spacemit,k1-syscon-rcpu
- spacemit,k1-syscon-rcpu2
- spacemit,k1-syscon-apbc2
- spacemit,k3-syscon-apbc
- spacemit,k3-syscon-apmu
- spacemit,k3-syscon-dciu
- spacemit,k3-syscon-mpmu
reg:
maxItems: 1
@@ -39,7 +43,8 @@ properties:
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K1 SoC, check <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
For K3 SoC, check <dt-bindings/clock/spacemit,k3-clocks.h> for valid indices.
"#power-domain-cells":
const: 1
@@ -66,6 +71,8 @@ allOf:
enum:
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
- spacemit,k3-syscon-apmu
- spacemit,k3-syscon-mpmu
then:
required:
- "#power-domain-cells"
@@ -80,6 +87,9 @@ allOf:
- spacemit,k1-syscon-apbc
- spacemit,k1-syscon-apmu
- spacemit,k1-syscon-mpmu
- spacemit,k3-syscon-apbc
- spacemit,k3-syscon-apmu
- spacemit,k3-syscon-mpmu
then:
required:
- clocks

9
MAINTAINERS
View File

@@ -3856,6 +3856,15 @@ L: rust-for-linux@vger.kernel.org
S: Maintained
F: drivers/net/phy/ax88796b_rust.rs
ARM/ASPEED CLOCK SUPPORT
M: Ryan Chen <ryan_chen@aspeedtech.com>
R: Joel Stanley <joel@jms.id.au>
L: linux-clk@vger.kernel.org
L: linux-aspeed@lists.ozlabs.org
S: Maintained
F: Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
F: drivers/clk/aspeed/
ASPEED CRYPTO DRIVER
M: Neal Liu <neal_liu@aspeedtech.com>
L: linux-aspeed@lists.ozlabs.org (moderated for non-subscribers)

2
drivers/clk/.kunitconfig
View File

@@ -1,4 +1,5 @@
CONFIG_KUNIT=y
CONFIG_KUNIT_UML_PCI=n
CONFIG_OF=y
CONFIG_OF_OVERLAY=y
CONFIG_COMMON_CLK=y
@@ -6,4 +7,3 @@ CONFIG_CLK_KUNIT_TEST=y
CONFIG_CLK_FIXED_RATE_KUNIT_TEST=y
CONFIG_CLK_GATE_KUNIT_TEST=y
CONFIG_CLK_FD_KUNIT_TEST=y
CONFIG_UML_PCI_OVER_VIRTIO=n

13
drivers/clk/Kconfig
View File

@@ -284,18 +284,6 @@ config COMMON_CLK_LAN966X
LAN966X SoC. GCK generates and supplies clock to various peripherals
within the SoC.
config COMMON_CLK_ASPEED
bool "Clock driver for Aspeed BMC SoCs"
depends on ARCH_ASPEED || COMPILE_TEST
default ARCH_ASPEED
select MFD_SYSCON
select RESET_CONTROLLER
help
This driver supports the SoC clocks on the Aspeed BMC platforms.
The G4 and G5 series, including the ast2400 and ast2500, are supported
by this driver.
config COMMON_CLK_S2MPS11
tristate "Clock driver for S2MPS1X/S5M8767 MFD"
depends on MFD_SEC_CORE || COMPILE_TEST
@@ -513,6 +501,7 @@ config COMMON_CLK_RPMI
source "drivers/clk/actions/Kconfig"
source "drivers/clk/analogbits/Kconfig"
source "drivers/clk/aspeed/Kconfig"
source "drivers/clk/baikal-t1/Kconfig"
source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig"

3
drivers/clk/Makefile
View File

@@ -62,8 +62,6 @@ obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o
obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o
obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o
obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
@@ -114,6 +112,7 @@ obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
# please keep this section sorted lexicographically by directory path name
obj-y += actions/
obj-y += analogbits/
obj-y += aspeed/
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_ARTPEC) += axis/
obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/

11
drivers/clk/actions/owl-composite.c
View File

@@ -57,15 +57,10 @@ static int owl_comp_div_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct owl_composite *comp = hw_to_owl_comp(hw);
long rate;
struct owl_divider_hw *div = &comp->rate.div_hw;
rate = owl_divider_helper_round_rate(&comp->common, &comp->rate.div_hw,
req->rate, &req->best_parent_rate);
if (rate < 0)
return rate;
req->rate = rate;
return 0;
return divider_determine_rate(&comp->common.hw, req, div->table,
div->width, div->div_flags);
}
static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,

17
drivers/clk/actions/owl-divider.c
View File

@@ -13,26 +13,13 @@
#include "owl-divider.h"
long owl_divider_helper_round_rate(struct owl_clk_common *common,
const struct owl_divider_hw *div_hw,
unsigned long rate,
unsigned long *parent_rate)
{
return divider_round_rate(&common->hw, rate, parent_rate,
div_hw->table, div_hw->width,
div_hw->div_flags);
}
static int owl_divider_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
struct owl_divider *div = hw_to_owl_divider(hw);
req->rate = owl_divider_helper_round_rate(&div->common, &div->div_hw,
req->rate,
&req->best_parent_rate);
return 0;
return divider_determine_rate(hw, req, div->div_hw.table,
div->div_hw.width, div->div_hw.div_flags);
}
unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,

5
drivers/clk/actions/owl-divider.h
View File

@@ -56,11 +56,6 @@ static inline struct owl_divider *hw_to_owl_divider(struct clk_hw *hw)
return container_of(common, struct owl_divider, common);
}
long owl_divider_helper_round_rate(struct owl_clk_common *common,
const struct owl_divider_hw *div_hw,
unsigned long rate,
unsigned long *parent_rate);
unsigned long owl_divider_helper_recalc_rate(struct owl_clk_common *common,
const struct owl_divider_hw *div_hw,
unsigned long parent_rate);

21
drivers/clk/aspeed/Kconfig Normal file
View File

@@ -0,0 +1,21 @@
# SPDX-License-Identifier: GPL-2.0-only
config COMMON_CLK_ASPEED
bool "Clock driver for Aspeed BMC SoCs"
depends on ARCH_ASPEED || COMPILE_TEST
default ARCH_ASPEED
select MFD_SYSCON
select RESET_CONTROLLER
help
This driver supports the SoC clocks on the Aspeed BMC platforms.
The G4 and G5 series, including the ast2400 and ast2500, are supported
by this driver.
config COMMON_CLK_AST2700
bool "Clock driver for AST2700 SoC"
depends on ARCH_ASPEED || COMPILE_TEST
help
This driver provides support for clock on AST2700 SoC.
The driver is responsible for managing the various clocks required
by the peripherals and cores within the AST2700.

4
drivers/clk/aspeed/Makefile Normal file
View File

@@ -0,0 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_COMMON_CLK_ASPEED) += clk-aspeed.o
obj-$(CONFIG_MACH_ASPEED_G6) += clk-ast2600.o
obj-$(CONFIG_COMMON_CLK_AST2700) += clk-ast2700.o

2
drivers/clk/clk-aspeed.c → drivers/clk/aspeed/clk-aspeed.c
View File

@@ -278,6 +278,8 @@ static const u8 aspeed_resets[] = {
[ASPEED_RESET_PECI] = 10,
[ASPEED_RESET_I2C] = 2,
[ASPEED_RESET_AHB] = 1,
[ASPEED_RESET_HACE] = 4,
[ASPEED_RESET_VIDEO] = 6,
/*
* SCUD4 resets start at an offset to separate them from

0
drivers/clk/clk-aspeed.h → drivers/clk/aspeed/clk-aspeed.h
View File

0
drivers/clk/clk-ast2600.c → drivers/clk/aspeed/clk-ast2600.c
View File

1055
drivers/clk/aspeed/clk-ast2700.c Normal file
View File

File diff suppressed because it is too large Load Diff

1
drivers/clk/clk-apple-nco.c
View File

@@ -320,6 +320,7 @@ static int applnco_probe(struct platform_device *pdev)
}
static const struct of_device_id applnco_ids[] = {
{ .compatible = "apple,t8103-nco" },
{ .compatible = "apple,nco" },
{ }
};

13
drivers/clk/clk-bm1880.c
View File

@@ -621,18 +621,11 @@ static int bm1880_clk_div_determine_rate(struct clk_hw *hw,
val = readl(reg_addr) >> div->shift;
val &= clk_div_mask(div->width);
req->rate = divider_ro_round_rate(hw, req->rate,
&req->best_parent_rate,
div->table,
div->width, div->flags, val);
return 0;
return divider_ro_determine_rate(hw, req, div->table,
div->width, div->flags, val);
}
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
div->table, div->width, div->flags);
return 0;
return divider_determine_rate(hw, req, div->table, div->width, div->flags);
}
static int bm1880_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,

4
drivers/clk/clk-lmk04832.c
View File

@@ -1400,7 +1400,6 @@ static int lmk04832_probe(struct spi_device *spi)
{
const struct lmk04832_device_info *info;
int rdbk_pin = RDBK_CLKIN_SEL1;
struct device_node *child;
struct lmk04832 *lmk;
u8 tmp[3];
int ret;
@@ -1462,14 +1461,13 @@ static int lmk04832_probe(struct spi_device *spi)
device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",
&lmk->sysref_pulse_cnt);
for_each_child_of_node(lmk->dev->of_node, child) {
for_each_child_of_node_scoped(lmk->dev->of_node, child) {
int reg;
ret = of_property_read_u32(child, "reg", &reg);
if (ret) {
dev_err(lmk->dev, "missing reg property in child: %s\n",
child->full_name);
of_node_put(child);
return ret;
}

5
drivers/clk/clk-loongson1.c
View File

@@ -99,10 +99,7 @@ static int ls1x_divider_determine_rate(struct clk_hw *hw,
struct ls1x_clk *ls1x_clk = to_ls1x_clk(hw);
const struct ls1x_clk_div_data *d = ls1x_clk->data;
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
d->table, d->width, d->flags);
return 0;
return divider_determine_rate(hw, req, d->table, d->width, d->flags);
}
static int ls1x_divider_set_rate(struct clk_hw *hw, unsigned long rate,

15
drivers/clk/clk-milbeaut.c
View File

@@ -398,19 +398,12 @@ static int m10v_clk_divider_determine_rate(struct clk_hw *hw,
val = readl(divider->reg) >> divider->shift;
val &= clk_div_mask(divider->width);
req->rate = divider_ro_round_rate(hw, req->rate,
&req->best_parent_rate,
divider->table,
divider->width,
divider->flags, val);
return 0;
return divider_ro_determine_rate(hw, req, divider->table,
divider->width, divider->flags,
val);
}
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
divider->table, divider->width, divider->flags);
return 0;
return divider_determine_rate(hw, req, divider->table, divider->width, divider->flags);
}
static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,

10
drivers/clk/clk-renesas-pcie.c
View File

@@ -64,7 +64,7 @@ struct rs9_driver_data {
struct i2c_client *client;
struct regmap *regmap;
const struct rs9_chip_info *chip_info;
struct clk_hw *clk_dif[4];
struct clk_hw *clk_dif[8];
u8 pll_amplitude;
u8 pll_ssc;
u8 clk_dif_sr;
@@ -354,7 +354,7 @@ static int rs9_probe(struct i2c_client *client)
return ret;
}
static int __maybe_unused rs9_suspend(struct device *dev)
static int rs9_suspend(struct device *dev)
{
struct rs9_driver_data *rs9 = dev_get_drvdata(dev);
@@ -364,7 +364,7 @@ static int __maybe_unused rs9_suspend(struct device *dev)
return 0;
}
static int __maybe_unused rs9_resume(struct device *dev)
static int rs9_resume(struct device *dev)
{
struct rs9_driver_data *rs9 = dev_get_drvdata(dev);
int ret;
@@ -410,12 +410,12 @@ static const struct of_device_id clk_rs9_of_match[] = {
};
MODULE_DEVICE_TABLE(of, clk_rs9_of_match);
static SIMPLE_DEV_PM_OPS(rs9_pm_ops, rs9_suspend, rs9_resume);
static DEFINE_SIMPLE_DEV_PM_OPS(rs9_pm_ops, rs9_suspend, rs9_resume);
static struct i2c_driver rs9_driver = {
.driver = {
.name = "clk-renesas-pcie-9series",
.pm = &rs9_pm_ops,
.pm = pm_sleep_ptr(&rs9_pm_ops),
.of_match_table = clk_rs9_of_match,
},
.probe = rs9_probe,

5
drivers/clk/clk-scpi.c
View File

@@ -265,20 +265,19 @@ static int scpi_clocks_probe(struct platform_device *pdev)
{
int ret;
struct device *dev = &pdev->dev;
struct device_node *child, *np = dev->of_node;
struct device_node *np = dev->of_node;
const struct of_device_id *match;
if (!get_scpi_ops())
return -ENXIO;
for_each_available_child_of_node(np, child) {
for_each_available_child_of_node_scoped(np, child) {
match = of_match_node(scpi_clk_match, child);
if (!match)
continue;
ret = scpi_clk_add(dev, child, match);
if (ret) {
scpi_clocks_remove(pdev);
of_node_put(child);
return ret;
}

7
drivers/clk/clk-versaclock3.c
View File

@@ -523,11 +523,8 @@ static int vc3_div_determine_rate(struct clk_hw *hw,
return 0;
}
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
div_data->table,
div_data->width, div_data->flags);
return 0;
return divider_determine_rate(hw, req, div_data->table, div_data->width,
div_data->flags);
}
static int vc3_div_set_rate(struct clk_hw *hw, unsigned long rate,

6
drivers/clk/hisilicon/clkdivider-hi6220.c
View File

@@ -60,10 +60,8 @@ static int hi6220_clkdiv_determine_rate(struct clk_hw *hw,
{
struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, dclk->table,
dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
return 0;
return divider_determine_rate(hw, req, dclk->table, dclk->width,
CLK_DIVIDER_ROUND_CLOSEST);
}
static int hi6220_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate,

4
drivers/clk/imx/clk-fracn-gppll.c
View File

@@ -88,7 +88,9 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20),
};
struct imx_fracn_gppll_clk imx_fracn_gppll = {

2
drivers/clk/mediatek/Kconfig
View File

@@ -820,7 +820,7 @@ config COMMON_CLK_MT8192
depends on ARM64 || COMPILE_TEST
select COMMON_CLK_MEDIATEK
select COMMON_CLK_MEDIATEK_FHCTL
default ARM64
default ARM64 && ARCH_MEDIATEK
help
This driver supports MediaTek MT8192 basic clocks.

2
drivers/clk/mediatek/clk-mt2701.c
View File

@@ -978,7 +978,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
mtk_clk_register_plls(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls),
clk_data);
mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
clk_data);

2
drivers/clk/mediatek/clk-mt2712-apmixedsys.c
View File

@@ -119,7 +119,7 @@ static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
if (r)
goto free_clk_data;

4
drivers/clk/mediatek/clk-mt6735-apmixedsys.c
View File

@@ -93,8 +93,8 @@ static int clk_mt6735_apmixed_probe(struct platform_device *pdev)
return -ENOMEM;
platform_set_drvdata(pdev, clk_data);
ret = mtk_clk_register_plls(pdev->dev.of_node, apmixedsys_plls,
ARRAY_SIZE(apmixedsys_plls), clk_data);
ret = mtk_clk_register_plls(&pdev->dev, apmixedsys_plls,
ARRAY_SIZE(apmixedsys_plls), clk_data);
if (ret) {
dev_err(&pdev->dev, "Failed to register PLLs: %d\n", ret);
return ret;

2
drivers/clk/mediatek/clk-mt6765.c
View File

@@ -740,7 +740,7 @@ static int clk_mt6765_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);

2
drivers/clk/mediatek/clk-mt6779.c
View File

@@ -1220,7 +1220,7 @@ static int clk_mt6779_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
ARRAY_SIZE(apmixed_clks), clk_data);

2
drivers/clk/mediatek/clk-mt6795-apmixedsys.c
View File

@@ -152,7 +152,7 @@ static int clk_mt6795_apmixed_probe(struct platform_device *pdev)
return -ENOMEM;
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
ret = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
ret = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (ret)
goto free_clk_data;

2
drivers/clk/mediatek/clk-mt6797.c
View File

@@ -655,7 +655,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
}

2
drivers/clk/mediatek/clk-mt7622-apmixedsys.c
View File

@@ -96,7 +96,7 @@ static int clk_mt7622_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;

2
drivers/clk/mediatek/clk-mt7629.c
View File

@@ -634,7 +634,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls),
clk_data);
mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,

2
drivers/clk/mediatek/clk-mt7981-apmixed.c
View File

@@ -76,7 +76,7 @@ static int clk_mt7981_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {

6
drivers/clk/mediatek/clk-mt7981-eth.c
View File

@@ -31,7 +31,7 @@ static const struct mtk_gate_regs sgmii0_cg_regs = {
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate sgmii0_clks[] __initconst = {
static const struct mtk_gate sgmii0_clks[] = {
GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),
GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),
GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),
@@ -53,7 +53,7 @@ static const struct mtk_gate_regs sgmii1_cg_regs = {
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate sgmii1_clks[] __initconst = {
static const struct mtk_gate sgmii1_clks[] = {
GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),
GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),
GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),
@@ -75,7 +75,7 @@ static const struct mtk_gate_regs eth_cg_regs = {
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
}
static const struct mtk_gate eth_clks[] __initconst = {
static const struct mtk_gate eth_clks[] = {
GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),
GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),
GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),

2
drivers/clk/mediatek/clk-mt7986-apmixed.c
View File

@@ -74,7 +74,7 @@ static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
if (r) {

2
drivers/clk/mediatek/clk-mt7988-apmixed.c
View File

@@ -86,7 +86,7 @@ static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
if (r)
goto free_apmixed_data;

3
drivers/clk/mediatek/clk-mt8135-apmixedsys.c
View File

@@ -57,7 +57,8 @@ static int clk_mt8135_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
ret = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls),
clk_data);
if (ret)
goto free_clk_data;

2
drivers/clk/mediatek/clk-mt8167-apmixedsys.c
View File

@@ -105,7 +105,7 @@ static int clk_mt8167_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;

14
drivers/clk/mediatek/clk-mt8173-apmixedsys.c
View File

@@ -140,13 +140,13 @@ MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_apmixed);
static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
{
const u8 *fhctl_node = "mediatek,mt8173-fhctl";
struct device_node *node = pdev->dev.of_node;
struct clk_hw_onecell_data *clk_data;
struct device *dev = &pdev->dev;
void __iomem *base;
struct clk_hw *hw;
int r;
base = of_iomap(node, 0);
base = of_iomap(dev->of_node, 0);
if (!base)
return -ENOMEM;
@@ -157,25 +157,25 @@ static int clk_mt8173_apmixed_probe(struct platform_device *pdev)
}
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
r = mtk_clk_register_pllfhs(dev, plls, ARRAY_SIZE(plls), pllfhs,
ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_clk_data;
hw = mtk_clk_register_ref2usb_tx("ref2usb_tx", "clk26m", base + REGOFF_REF2USB);
if (IS_ERR(hw)) {
r = PTR_ERR(hw);
dev_err(&pdev->dev, "Failed to register ref2usb_tx: %d\n", r);
dev_err(dev, "Failed to register ref2usb_tx: %d\n", r);
goto unregister_plls;
}
clk_data->hws[CLK_APMIXED_REF2USB_TX] = hw;
hw = devm_clk_hw_register_divider(&pdev->dev, "hdmi_ref", "tvdpll_594m", 0,
hw = devm_clk_hw_register_divider(dev, "hdmi_ref", "tvdpll_594m", 0,
base + REGOFF_HDMI_REF, 16, 3,
CLK_DIVIDER_POWER_OF_TWO, NULL);
clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;
r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
r = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get, clk_data);
if (r)
goto unregister_ref2usb;

2
drivers/clk/mediatek/clk-mt8183-apmixedsys.c
View File

@@ -155,7 +155,7 @@ static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;

2
drivers/clk/mediatek/clk-mt8186-apmixedsys.c
View File

@@ -151,7 +151,7 @@ static int clk_mt8186_apmixed_probe(struct platform_device *pdev)
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_apmixed_data;

2
drivers/clk/mediatek/clk-mt8188-apmixedsys.c
View File

@@ -106,7 +106,7 @@ static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
r = mtk_clk_register_plls(&pdev->dev, plls, ARRAY_SIZE(plls), clk_data);
if (r)
goto free_apmixed_data;

2
drivers/clk/mediatek/clk-mt8192-apmixedsys.c
View File

@@ -162,7 +162,7 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_clk_data;

2
drivers/clk/mediatek/clk-mt8195-apmixedsys.c
View File

@@ -181,7 +181,7 @@ static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
r = mtk_clk_register_pllfhs(&pdev->dev, plls, ARRAY_SIZE(plls),
pllfhs, ARRAY_SIZE(pllfhs), clk_data);
if (r)
goto free_apmixed_data;

3
drivers/clk/mediatek/clk-mt8195-apusys_pll.c
View File

@@ -66,7 +66,8 @@ static int clk_mt8195_apusys_pll_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, apusys_plls, ARRAY_SIZE(apusys_plls), clk_data);
r = mtk_clk_register_plls(&pdev->dev, apusys_plls,
ARRAY_SIZE(apusys_plls), clk_data);
if (r)
goto free_apusys_pll_data;

3
drivers/clk/mediatek/clk-mt8196-apmixedsys.c
View File

@@ -152,7 +152,8 @@ static int clk_mt8196_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, mcd->clks, mcd->num_clks, clk_data);
r = mtk_clk_register_plls(&pdev->dev, mcd->clks, mcd->num_clks,
clk_data);
if (r)
goto free_apmixed_data;

2
drivers/clk/mediatek/clk-mt8196-mcu.c
View File

@@ -122,7 +122,7 @@ static int clk_mt8196_mcu_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
r = mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data);
if (r)
goto free_clk_data;

15
drivers/clk/mediatek/clk-mt8196-mfg.c
View File

@@ -58,24 +58,25 @@
.pcw_shift = _pcw_shift, \
.pcwbits = _pcwbits, \
.pcwibits = MT8196_INTEGER_BITS, \
.parent_name = "mfg_eb", \
}
static const struct mtk_pll_data mfg_ao_plls[] = {
PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0, 0,
BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
PLL(CLK_MFG_AO_MFGPLL, "mfgpll", MFGPLL_CON0, MFGPLL_CON0, 0, 0,
PLL_PARENT_EN, BIT(0), MFGPLL_CON1, 24, 0, 0, 0,
MFGPLL_CON1, 0, 22),
};
static const struct mtk_pll_data mfgsc0_ao_plls[] = {
PLL(CLK_MFGSC0_AO_MFGPLL_SC0, "mfgpll-sc0", MFGPLL_SC0_CON0,
MFGPLL_SC0_CON0, 0, 0, 0, BIT(0), MFGPLL_SC0_CON1, 24, 0, 0, 0,
MFGPLL_SC0_CON1, 0, 22),
MFGPLL_SC0_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC0_CON1, 24,
0, 0, 0, MFGPLL_SC0_CON1, 0, 22),
};
static const struct mtk_pll_data mfgsc1_ao_plls[] = {
PLL(CLK_MFGSC1_AO_MFGPLL_SC1, "mfgpll-sc1", MFGPLL_SC1_CON0,
MFGPLL_SC1_CON0, 0, 0, 0, BIT(0), MFGPLL_SC1_CON1, 24, 0, 0, 0,
MFGPLL_SC1_CON1, 0, 22),
MFGPLL_SC1_CON0, 0, 0, PLL_PARENT_EN, BIT(0), MFGPLL_SC1_CON1, 24,
0, 0, 0, MFGPLL_SC1_CON1, 0, 22),
};
static const struct of_device_id of_match_clk_mt8196_mfg[] = {
@@ -105,7 +106,7 @@ static int clk_mt8196_mfg_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
r = mtk_clk_register_plls(node, plls, num_plls, clk_data);
r = mtk_clk_register_plls(&pdev->dev, plls, num_plls, clk_data);
if (r)
goto free_clk_data;

2
drivers/clk/mediatek/clk-mt8196-vlpckgen.c
View File

@@ -664,7 +664,7 @@ static int clk_mt8196_vlp_probe(struct platform_device *pdev)
if (r)
goto unregister_factors;
r = mtk_clk_register_plls(node, vlp_plls, ARRAY_SIZE(vlp_plls),
r = mtk_clk_register_plls(dev, vlp_plls, ARRAY_SIZE(vlp_plls),
clk_data);
if (r)
goto unregister_muxes;

2
drivers/clk/mediatek/clk-mt8365-apmixedsys.c
View File

@@ -133,7 +133,7 @@ static int clk_mt8365_apmixed_probe(struct platform_device *pdev)
return PTR_ERR(hw);
clk_data->hws[CLK_APMIXED_USB20_EN] = hw;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;

2
drivers/clk/mediatek/clk-mt8516-apmixedsys.c
View File

@@ -87,7 +87,7 @@ static int clk_mt8516_apmixed_probe(struct platform_device *pdev)
if (!clk_data)
return -ENOMEM;
ret = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
ret = mtk_clk_register_plls(dev, plls, ARRAY_SIZE(plls), clk_data);
if (ret)
return ret;

2
drivers/clk/mediatek/clk-mt8516.c
View File

@@ -544,7 +544,7 @@ static const struct mtk_gate_regs top5_cg_regs = {
#define GATE_TOP5(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &top5_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate top_clks[] __initconst = {
static const struct mtk_gate top_clks[] = {
/* TOP1 */
GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),

12
drivers/clk/mediatek/clk-mtk.c
View File

@@ -497,14 +497,16 @@ static int __mtk_clk_simple_probe(struct platform_device *pdev,
if (mcd->need_runtime_pm) {
devm_pm_runtime_enable(&pdev->dev);
r = devm_pm_runtime_enable(&pdev->dev);
if (r)
goto unmap_io;
/*
* Do a pm_runtime_resume_and_get() to workaround a possible
* deadlock between clk_register() and the genpd framework.
*/
r = pm_runtime_resume_and_get(&pdev->dev);
if (r)
return r;
goto unmap_io;
}
/* Calculate how many clk_hw_onecell_data entries to allocate */
@@ -618,11 +620,11 @@ unregister_fixed_clks:
free_data:
mtk_free_clk_data(clk_data);
free_base:
if (mcd->shared_io && base)
iounmap(base);
if (mcd->need_runtime_pm)
pm_runtime_put(&pdev->dev);
unmap_io:
if (mcd->shared_io && base)
iounmap(base);
return r;
}

19
drivers/clk/mediatek/clk-pll.c
View File

@@ -11,6 +11,7 @@
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include "clk-pll.h"
@@ -358,6 +359,9 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
init.name = data->name;
init.flags = (data->flags & PLL_AO) ? CLK_IS_CRITICAL : 0;
if (data->flags & PLL_PARENT_EN)
init.flags |= CLK_OPS_PARENT_ENABLE;
init.ops = pll_ops;
if (data->parent_name)
init.parent_names = &data->parent_name;
@@ -365,7 +369,7 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
init.parent_names = &parent_name;
init.num_parents = 1;
ret = clk_hw_register(NULL, &pll->hw);
ret = clk_hw_register(pll->dev, &pll->hw);
if (ret)
return ERR_PTR(ret);
@@ -373,7 +377,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
return &pll->hw;
}
struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
struct clk_hw *mtk_clk_register_pll(struct device *dev,
const struct mtk_pll_data *data,
void __iomem *base)
{
struct mtk_clk_pll *pll;
@@ -384,6 +389,8 @@ struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
if (!pll)
return ERR_PTR(-ENOMEM);
pll->dev = dev;
hw = mtk_clk_register_pll_ops(pll, data, base, pll_ops);
if (IS_ERR(hw))
kfree(pll);
@@ -404,7 +411,7 @@ void mtk_clk_unregister_pll(struct clk_hw *hw)
kfree(pll);
}
int mtk_clk_register_plls(struct device_node *node,
int mtk_clk_register_plls(struct device *dev,
const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data)
{
@@ -412,7 +419,7 @@ int mtk_clk_register_plls(struct device_node *node,
int i;
struct clk_hw *hw;
base = of_iomap(node, 0);
base = of_iomap(dev->of_node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return -EINVAL;
@@ -423,11 +430,11 @@ int mtk_clk_register_plls(struct device_node *node,
if (!IS_ERR_OR_NULL(clk_data->hws[pll->id])) {
pr_warn("%pOF: Trying to register duplicate clock ID: %d\n",
node, pll->id);
dev->of_node, pll->id);
continue;
}
hw = mtk_clk_register_pll(pll, base);
hw = mtk_clk_register_pll(dev, pll, base);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %pe\n", pll->name,

15
drivers/clk/mediatek/clk-pll.h
View File

@@ -10,9 +10,7 @@
#include <linux/clk-provider.h>
#include <linux/types.h>
struct clk_ops;
struct clk_hw_onecell_data;
struct device_node;
struct device;
struct mtk_pll_div_table {
u32 div;
@@ -21,6 +19,7 @@ struct mtk_pll_div_table {
#define HAVE_RST_BAR BIT(0)
#define PLL_AO BIT(1)
#define PLL_PARENT_EN BIT(2)
#define POSTDIV_MASK GENMASK(2, 0)
struct mtk_pll_data {
@@ -63,6 +62,7 @@ struct mtk_pll_data {
*/
struct mtk_clk_pll {
struct device *dev;
struct clk_hw hw;
void __iomem *base_addr;
void __iomem *pd_addr;
@@ -78,9 +78,9 @@ struct mtk_clk_pll {
const struct mtk_pll_data *data;
};
int mtk_clk_register_plls(struct device_node *node,
const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data);
int mtk_clk_register_plls(struct device *dev, const struct mtk_pll_data *plls,
int num_plls, struct clk_hw_onecell_data *clk_data);
void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
struct clk_hw_onecell_data *clk_data);
@@ -110,7 +110,8 @@ struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
const struct mtk_pll_data *data,
void __iomem *base,
const struct clk_ops *pll_ops);
struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
struct clk_hw *mtk_clk_register_pll(struct device *dev,
const struct mtk_pll_data *data,
void __iomem *base);
void mtk_clk_unregister_pll(struct clk_hw *hw);

13
drivers/clk/mediatek/clk-pllfh.c
View File

@@ -10,6 +10,7 @@
#include <linux/slab.h>
#include <linux/clkdev.h>
#include <linux/delay.h>
#include <linux/device.h>
#include "clk-mtk.h"
#include "clk-pllfh.h"
@@ -149,7 +150,7 @@ static bool fhctl_is_supported_and_enabled(const struct mtk_pllfh_data *pllfh)
}
static struct clk_hw *
mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_data,
struct mtk_pllfh_data *pllfh_data, void __iomem *base)
{
struct clk_hw *hw;
@@ -166,6 +167,8 @@ mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data,
goto out;
}
fh->clk_pll.dev = dev;
hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base,
&mtk_pllfh_ops);
@@ -194,7 +197,7 @@ static void mtk_clk_unregister_pllfh(struct clk_hw *hw)
kfree(fh);
}
int mtk_clk_register_pllfhs(struct device_node *node,
int mtk_clk_register_pllfhs(struct device *dev,
const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_fhs,
struct clk_hw_onecell_data *clk_data)
@@ -203,7 +206,7 @@ int mtk_clk_register_pllfhs(struct device_node *node,
int i;
struct clk_hw *hw;
base = of_iomap(node, 0);
base = of_iomap(dev->of_node, 0);
if (!base) {
pr_err("%s(): ioremap failed\n", __func__);
return -EINVAL;
@@ -218,9 +221,9 @@ int mtk_clk_register_pllfhs(struct device_node *node,
use_fhctl = fhctl_is_supported_and_enabled(pllfh);
if (use_fhctl)
hw = mtk_clk_register_pllfh(pll, pllfh, base);
hw = mtk_clk_register_pllfh(dev, pll, pllfh, base);
else
hw = mtk_clk_register_pll(pll, base);
hw = mtk_clk_register_pll(dev, pll, base);
if (IS_ERR(hw)) {
pr_err("Failed to register %s clk %s: %ld\n",

2
drivers/clk/mediatek/clk-pllfh.h
View File

@@ -68,7 +68,7 @@ struct fh_operation {
int (*ssc_enable)(struct mtk_fh *fh, u32 rate);
};
int mtk_clk_register_pllfhs(struct device_node *node,
int mtk_clk_register_pllfhs(struct device *dev,
const struct mtk_pll_data *plls, int num_plls,
struct mtk_pllfh_data *pllfhs, int num_pllfhs,
struct clk_hw_onecell_data *clk_data);

28
drivers/clk/meson/Kconfig
View File

@@ -201,4 +201,32 @@ config COMMON_CLK_S4_PERIPHERALS
help
Support for the peripherals clock controller on Amlogic S805X2 and S905Y4
devices, AKA S4. Say Y if you want S4 peripherals clock controller to work.
config COMMON_CLK_T7_PLL
tristate "Amlogic T7 SoC PLL controller support"
depends on ARM64
default ARCH_MESON
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_MPLL
select COMMON_CLK_MESON_PLL
imply COMMON_CLK_SCMI
help
Support for the PLL clock controller on Amlogic A311D2 based
device, AKA T7. PLLs are required by most peripheral to operate.
Say Y if you want T7 PLL clock controller to work.
config COMMON_CLK_T7_PERIPHERALS
tristate "Amlogic T7 SoC peripherals clock controller support"
depends on ARM64
default ARCH_MESON
select COMMON_CLK_MESON_REGMAP
select COMMON_CLK_MESON_CLKC_UTILS
select COMMON_CLK_MESON_DUALDIV
imply COMMON_CLK_SCMI
imply COMMON_CLK_T7_PLL
help
Support for the peripherals clock controller on Amlogic A311D2 based
device, AKA T7. Peripherals are required by most peripheral to operate.
Say Y if you want T7 peripherals clock controller to work.
endmenu

2
drivers/clk/meson/Makefile
View File

@@ -26,3 +26,5 @@ obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
obj-$(CONFIG_COMMON_CLK_S4_PLL) += s4-pll.o
obj-$(CONFIG_COMMON_CLK_S4_PERIPHERALS) += s4-peripherals.o
obj-$(CONFIG_COMMON_CLK_T7_PLL) += t7-pll.o
obj-$(CONFIG_COMMON_CLK_T7_PERIPHERALS) += t7-peripherals.o

17
drivers/clk/meson/g12a.c
View File

@@ -777,12 +777,23 @@ static struct clk_regmap g12a_hdmi_pll_dco = {
},
};
/*
* G12/SM1 hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.
* A divider value of 3 should map to /8 but instead map /4 so ignore it.
*/
static const struct clk_div_table g12a_hdmi_pll_od_div_table[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ /* sentinel */ }
};
static struct clk_regmap g12a_hdmi_pll_od = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_HDMI_PLL_CNTL0,
.shift = 16,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
.table = g12a_hdmi_pll_od_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od",
@@ -800,7 +811,7 @@ static struct clk_regmap g12a_hdmi_pll_od2 = {
.offset = HHI_HDMI_PLL_CNTL0,
.shift = 18,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
.table = g12a_hdmi_pll_od_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od2",
@@ -818,7 +829,7 @@ static struct clk_regmap g12a_hdmi_pll = {
.offset = HHI_HDMI_PLL_CNTL0,
.shift = 20,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
.table = g12a_hdmi_pll_od_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll",

23
drivers/clk/meson/gxbb.c
View File

@@ -349,12 +349,23 @@ static struct clk_regmap gxbb_hdmi_pll = {
},
};
/*
* GXL hdmi OD dividers are POWER_OF_TWO dividers but limited to /4.
* A divider value of 3 should map to /8 but instead map /4 so ignore it.
*/
static const struct clk_div_table gxl_hdmi_pll_od_div_table[] = {
{ .val = 0, .div = 1 },
{ .val = 1, .div = 2 },
{ .val = 2, .div = 4 },
{ /* sentinel */ }
};
static struct clk_regmap gxl_hdmi_pll_od = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_HDMI_PLL_CNTL + 8,
.offset = HHI_HDMI_PLL_CNTL3,
.shift = 21,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
.table = gxl_hdmi_pll_od_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od",
@@ -369,10 +380,10 @@ static struct clk_regmap gxl_hdmi_pll_od = {
static struct clk_regmap gxl_hdmi_pll_od2 = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_HDMI_PLL_CNTL + 8,
.offset = HHI_HDMI_PLL_CNTL3,
.shift = 23,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
.table = gxl_hdmi_pll_od_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll_od2",
@@ -387,10 +398,10 @@ static struct clk_regmap gxl_hdmi_pll_od2 = {
static struct clk_regmap gxl_hdmi_pll = {
.data = &(struct clk_regmap_div_data){
.offset = HHI_HDMI_PLL_CNTL + 8,
.offset = HHI_HDMI_PLL_CNTL3,
.shift = 19,
.width = 2,
.flags = CLK_DIVIDER_POWER_OF_TWO,
.table = gxl_hdmi_pll_od_div_table,
},
.hw.init = &(struct clk_init_data){
.name = "hdmi_pll",

206
drivers/clk/meson/s4-peripherals.c
View File

@@ -44,6 +44,7 @@
#define CLKCTRL_VDIN_MEAS_CLK_CTRL 0x0f8
#define CLKCTRL_VAPBCLK_CTRL 0x0fc
#define CLKCTRL_HDCP22_CTRL 0x100
#define CLKCTRL_CDAC_CLK_CTRL 0x108
#define CLKCTRL_VDEC_CLK_CTRL 0x140
#define CLKCTRL_VDEC2_CLK_CTRL 0x144
#define CLKCTRL_VDEC3_CLK_CTRL 0x148
@@ -1106,7 +1107,6 @@ static struct clk_regmap s4_cts_enci_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = s4_cts_parents,
.num_parents = ARRAY_SIZE(s4_cts_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1122,7 +1122,21 @@ static struct clk_regmap s4_cts_encp_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = s4_cts_parents,
.num_parents = ARRAY_SIZE(s4_cts_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_cts_encl_sel = {
.data = &(struct clk_regmap_mux_data){
.offset = CLKCTRL_VIID_CLK_DIV,
.mask = 0xf,
.shift = 12,
.table = s4_cts_parents_val_table,
},
.hw.init = &(struct clk_init_data){
.name = "cts_encl_sel",
.ops = &clk_regmap_mux_ops,
.parent_hws = s4_cts_parents,
.num_parents = ARRAY_SIZE(s4_cts_parents),
},
};
@@ -1138,7 +1152,6 @@ static struct clk_regmap s4_cts_vdac_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = s4_cts_parents,
.num_parents = ARRAY_SIZE(s4_cts_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1169,7 +1182,6 @@ static struct clk_regmap s4_hdmi_tx_sel = {
.ops = &clk_regmap_mux_ops,
.parent_hws = s4_hdmi_tx_parents,
.num_parents = ARRAY_SIZE(s4_hdmi_tx_parents),
.flags = CLK_SET_RATE_PARENT,
},
};
@@ -1205,6 +1217,22 @@ static struct clk_regmap s4_cts_encp = {
},
};
static struct clk_regmap s4_cts_encl = {
.data = &(struct clk_regmap_gate_data){
.offset = CLKCTRL_VID_CLK_CTRL2,
.bit_idx = 3,
},
.hw.init = &(struct clk_init_data) {
.name = "cts_encl",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_cts_encl_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_cts_vdac = {
.data = &(struct clk_regmap_gate_data){
.offset = CLKCTRL_VID_CLK_CTRL2,
@@ -2735,6 +2763,165 @@ static struct clk_regmap s4_gen_clk = {
},
};
/* CVBS DAC */
static struct clk_regmap s4_cdac_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = CLKCTRL_CDAC_CLK_CTRL,
.mask = 0x3,
.shift = 16,
},
.hw.init = &(struct clk_init_data){
.name = "cdac_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal", },
{ .fw_name = "fclk_div5" },
},
.num_parents = 2,
},
};
static struct clk_regmap s4_cdac_div = {
.data = &(struct clk_regmap_div_data) {
.offset = CLKCTRL_CDAC_CLK_CTRL,
.shift = 0,
.width = 16,
},
.hw.init = &(struct clk_init_data){
.name = "cdac_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_cdac_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_cdac = {
.data = &(struct clk_regmap_gate_data) {
.offset = CLKCTRL_CDAC_CLK_CTRL,
.bit_idx = 20,
},
.hw.init = &(struct clk_init_data){
.name = "cdac",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_cdac_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_demod_core_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.mask = 0x3,
.shift = 9,
},
.hw.init = &(struct clk_init_data){
.name = "demod_core_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal" },
{ .fw_name = "fclk_div7" },
{ .fw_name = "fclk_div4" }
},
.num_parents = 3,
},
};
static struct clk_regmap s4_demod_core_div = {
.data = &(struct clk_regmap_div_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.shift = 0,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "demod_core_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_demod_core_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_demod_core = {
.data = &(struct clk_regmap_gate_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.bit_idx = 8
},
.hw.init = &(struct clk_init_data){
.name = "demod_core",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_demod_core_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
/* CVBS ADC */
static struct clk_regmap s4_adc_extclk_in_sel = {
.data = &(struct clk_regmap_mux_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.mask = 0x7,
.shift = 25,
},
.hw.init = &(struct clk_init_data){
.name = "adc_extclk_in_sel",
.ops = &clk_regmap_mux_ops,
.parent_data = (const struct clk_parent_data []) {
{ .fw_name = "xtal" },
{ .fw_name = "fclk_div4" },
{ .fw_name = "fclk_div3" },
{ .fw_name = "fclk_div5" },
{ .fw_name = "fclk_div7" },
{ .fw_name = "mpll2" },
{ .fw_name = "gp0_pll" },
{ .fw_name = "hifi_pll" }
},
.num_parents = 8,
},
};
static struct clk_regmap s4_adc_extclk_in_div = {
.data = &(struct clk_regmap_div_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.shift = 16,
.width = 7,
},
.hw.init = &(struct clk_init_data){
.name = "adc_extclk_in_div",
.ops = &clk_regmap_divider_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_adc_extclk_in_sel.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static struct clk_regmap s4_adc_extclk_in = {
.data = &(struct clk_regmap_gate_data) {
.offset = CLKCTRL_DEMOD_CLK_CTRL,
.bit_idx = 24
},
.hw.init = &(struct clk_init_data){
.name = "adc_extclk_in",
.ops = &clk_regmap_gate_ops,
.parent_hws = (const struct clk_hw *[]) {
&s4_adc_extclk_in_div.hw
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
static const struct clk_parent_data s4_pclk_parents = { .hw = &s4_sys_clk.hw };
#define S4_PCLK(_name, _reg, _bit, _flags) \
@@ -3028,6 +3215,17 @@ static struct clk_hw *s4_peripherals_hw_clks[] = {
[CLKID_HDCP22_SKPCLK_SEL] = &s4_hdcp22_skpclk_sel.hw,
[CLKID_HDCP22_SKPCLK_DIV] = &s4_hdcp22_skpclk_div.hw,
[CLKID_HDCP22_SKPCLK] = &s4_hdcp22_skpclk.hw,
[CLKID_CTS_ENCL_SEL] = &s4_cts_encl_sel.hw,
[CLKID_CTS_ENCL] = &s4_cts_encl.hw,
[CLKID_CDAC_SEL] = &s4_cdac_sel.hw,
[CLKID_CDAC_DIV] = &s4_cdac_div.hw,
[CLKID_CDAC] = &s4_cdac.hw,
[CLKID_DEMOD_CORE_SEL] = &s4_demod_core_sel.hw,
[CLKID_DEMOD_CORE_DIV] = &s4_demod_core_div.hw,
[CLKID_DEMOD_CORE] = &s4_demod_core.hw,
[CLKID_ADC_EXTCLK_IN_SEL] = &s4_adc_extclk_in_sel.hw,
[CLKID_ADC_EXTCLK_IN_DIV] = &s4_adc_extclk_in_div.hw,
[CLKID_ADC_EXTCLK_IN] = &s4_adc_extclk_in.hw,
};
static const struct meson_clkc_data s4_peripherals_clkc_data = {

1271
drivers/clk/meson/t7-peripherals.c Normal file
View File

File diff suppressed because it is too large Load Diff

1074
drivers/clk/meson/t7-pll.c Normal file
View File

File diff suppressed because it is too large Load Diff

4
drivers/clk/microchip/Kconfig
View File

@@ -5,8 +5,8 @@ config COMMON_CLK_PIC32
config MCHP_CLK_MPFS
bool "Clk driver for PolarFire SoC"
depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST
default ARCH_MICROCHIP_POLARFIRE
depends on ARCH_MICROCHIP || COMPILE_TEST
default y
depends on MFD_SYSCON
select AUXILIARY_BUS
select REGMAP_MMIO

36
drivers/clk/microchip/clk-core.c
View File

@@ -10,7 +10,6 @@
#include <linux/io.h>
#include <linux/iopoll.h>
#include <asm/mach-pic32/pic32.h>
#include <asm/traps.h>
#include "clk-core.h"
@@ -283,14 +282,13 @@ static u8 roclk_get_parent(struct clk_hw *hw)
v = (readl(refo->ctrl_reg) >> REFO_SEL_SHIFT) & REFO_SEL_MASK;
if (!refo->parent_map)
return v;
if (refo->parent_map) {
for (i = 0; i < clk_hw_get_num_parents(hw); i++)
if (refo->parent_map[i] == v)
return i;
}
for (i = 0; i < clk_hw_get_num_parents(hw); i++)
if (refo->parent_map[i] == v)
return i;
return -EINVAL;
return v;
}
static unsigned long roclk_calc_rate(unsigned long parent_rate,
@@ -780,15 +778,6 @@ static unsigned long sclk_get_rate(struct clk_hw *hw, unsigned long parent_rate)
return parent_rate / div;
}
static int sclk_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
req->rate = calc_best_divided_rate(req->rate, req->best_parent_rate,
SLEW_SYSDIV, 1);
return 0;
}
static int sclk_set_rate(struct clk_hw *hw,
unsigned long rate, unsigned long parent_rate)
{
@@ -826,13 +815,13 @@ static u8 sclk_get_parent(struct clk_hw *hw)
v = (readl(sclk->mux_reg) >> OSC_CUR_SHIFT) & OSC_CUR_MASK;
if (!sclk->parent_map)
return v;
if (sclk->parent_map) {
for (i = 0; i < clk_hw_get_num_parents(hw); i++)
if (sclk->parent_map[i] == v)
return i;
}
for (i = 0; i < clk_hw_get_num_parents(hw); i++)
if (sclk->parent_map[i] == v)
return i;
return -EINVAL;
return v;
}
static int sclk_set_parent(struct clk_hw *hw, u8 index)
@@ -912,7 +901,6 @@ static int sclk_init(struct clk_hw *hw)
const struct clk_ops pic32_sclk_ops = {
.get_parent = sclk_get_parent,
.set_parent = sclk_set_parent,
.determine_rate = sclk_determine_rate,
.set_rate = sclk_set_rate,
.recalc_rate = sclk_get_rate,
.init = sclk_init,

7
drivers/clk/nuvoton/clk-ma35d1-divider.c
View File

@@ -44,11 +44,8 @@ static int ma35d1_clkdiv_determine_rate(struct clk_hw *hw,
{
struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
dclk->table, dclk->width,
CLK_DIVIDER_ROUND_CLOSEST);
return 0;
return divider_determine_rate(hw, req, dclk->table, dclk->width,
CLK_DIVIDER_ROUND_CLOSEST);
}
static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)

6
drivers/clk/nxp/clk-lpc32xx.c
View File

@@ -975,10 +975,8 @@ static int clk_divider_determine_rate(struct clk_hw *hw,
return 0;
}
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
divider->table, divider->width, divider->flags);
return 0;
return divider_determine_rate(hw, req, divider->table, divider->width,
divider->flags);
}
static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,

71
drivers/clk/qcom/Kconfig
View File

@@ -46,6 +46,61 @@ config CLK_GLYMUR_TCSRCC
Support for the TCSR clock controller on GLYMUR devices.
Say Y if you want to use peripheral devices such as USB/PCIe/EDP.
config CLK_KAANAPALI_CAMCC
tristate "Kaanapali Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_KAANAPALI_GCC
help
Support for the camera clock controller on Qualcomm Technologies, Inc
Kaanapali devices.
Say Y if you want to support camera devices and functionality such as
capturing pictures.
config CLK_KAANAPALI_DISPCC
tristate "Kaanapali Display Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_KAANAPALI_GCC
help
Support for the display clock controller on Qualcomm Technologies, Inc
Kaanapali devices.
Say Y if you want to support display devices and functionality such as
splash screen.
config CLK_KAANAPALI_GCC
tristate "Kaanapali Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on Kaanapali devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config CLK_KAANAPALI_GPUCC
tristate "Kaanapali Graphics Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_KAANAPALI_GCC
help
Support for the graphics clock controller on Kaanapali devices.
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
config CLK_KAANAPALI_TCSRCC
tristate "Kaanapali TCSR Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the TCSR clock controller on Kaanapali devices.
Say Y if you want to use peripheral devices such as PCIe, USB, UFS.
config CLK_KAANAPALI_VIDEOCC
tristate "Kaanapali Video Clock Controller"
depends on ARM64 || COMPILE_TEST
select CLK_KAANAPALI_GCC
help
Support for the video clock controller on Kaanapali devices.
Say Y if you want to support video devices and functionality such as
video encode/decode.
config CLK_X1E80100_CAMCC
tristate "X1E80100 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
@@ -370,12 +425,12 @@ config MSM_GCC_8916
SD/eMMC, display, graphics, camera etc.
config MSM_GCC_8917
tristate "MSM89(17/37)/QM215 Global Clock Controller"
tristate "MSM89(17/37/40)/QM215/SDM439 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on msm8917, msm8937
and qm215 devices.
Support for the global clock controller on msm8917, msm8937,
msm8940, qm215 and sdm439 devices.
Say Y if you want to use devices such as UART, SPI i2c, USB,
SD/eMMC, display, graphics, camera etc.
@@ -1069,6 +1124,16 @@ config SM_CAMCC_8650
Support for the camera clock controller on SM8650 devices.
Say Y if you want to support camera devices and camera functionality.
config SM_CAMCC_8750
tristate "SM8750 Camera Clock Controller"
depends on ARM64 || COMPILE_TEST
select SM_GCC_8750
help
Support for the camera clock controller on SM8750 devices.
The camera clock controller has a separate cambist controller which
controls the mclk of the camera clocks.
Say Y if you want to support camera devices and camera functionality.
config SM_DISPCC_4450
tristate "SM4450 Display Clock Controller"
depends on ARM64 || COMPILE_TEST

7
drivers/clk/qcom/Makefile
View File

@@ -24,6 +24,12 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
obj-$(CONFIG_CLK_KAANAPALI_CAMCC) += cambistmclkcc-kaanapali.o camcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_DISPCC) += dispcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GCC) += gcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_GPUCC) += gpucc-kaanapali.o gxclkctl-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_TCSRCC) += tcsrcc-kaanapali.o
obj-$(CONFIG_CLK_KAANAPALI_VIDEOCC) += videocc-kaanapali.o
obj-$(CONFIG_CLK_X1E80100_CAMCC) += camcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_DISPCC) += dispcc-x1e80100.o
obj-$(CONFIG_CLK_X1E80100_GCC) += gcc-x1e80100.o
@@ -136,6 +142,7 @@ obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
obj-$(CONFIG_SM_CAMCC_8550) += camcc-sm8550.o
obj-$(CONFIG_SM_CAMCC_8650) += camcc-sm8650.o
obj-$(CONFIG_SM_CAMCC_8750) += cambistmclkcc-sm8750.o camcc-sm8750.o
obj-$(CONFIG_SM_CAMCC_MILOS) += camcc-milos.o
obj-$(CONFIG_SM_DISPCC_4450) += dispcc-sm4450.o
obj-$(CONFIG_SM_DISPCC_6115) += dispcc-sm6115.o

437
drivers/clk/qcom/cambistmclkcc-kaanapali.c Normal file
View File

@@ -0,0 +1,437 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-pll.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "clk-regmap-divider.h"
#include "clk-regmap-mux.h"
#include "common.h"
#include "gdsc.h"
#include "reset.h"
enum {
DT_AHB_CLK,
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_SLEEP_CLK,
};
enum {
P_BI_TCXO,
P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN,
P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN,
};
static const struct pll_vco rivian_eko_t_vco[] = {
{ 883200000, 1171200000, 0 },
};
/* 960.0 MHz Configuration */
static const struct alpha_pll_config cam_bist_mclk_cc_pll0_config = {
.l = 0x32,
.cal_l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x12000000,
.config_ctl_hi_val = 0x00890263,
.config_ctl_hi1_val = 0x1af04237,
.config_ctl_hi2_val = 0x00000000,
};
static struct clk_alpha_pll cam_bist_mclk_cc_pll0 = {
.offset = 0x0,
.config = &cam_bist_mclk_cc_pll0_config,
.vco_table = rivian_eko_t_vco,
.num_vco = ARRAY_SIZE(rivian_eko_t_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_rivian_eko_t_ops,
},
},
};
static const struct parent_map cam_bist_mclk_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 3 },
{ P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data cam_bist_mclk_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_bist_mclk_cc_pll0.clkr.hw },
{ .hw = &cam_bist_mclk_cc_pll0.clkr.hw },
};
static const struct freq_tbl ftbl_cam_bist_mclk_cc_mclk0_clk_src[] = {
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 10, 1, 4),
F(68571429, P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 14, 0, 0),
{ }
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk0_clk_src = {
.cmd_rcgr = 0x4000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.hw_clk_ctrl = true,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk0_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk1_clk_src = {
.cmd_rcgr = 0x401c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.hw_clk_ctrl = true,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk1_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk2_clk_src = {
.cmd_rcgr = 0x4038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.hw_clk_ctrl = true,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk2_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk3_clk_src = {
.cmd_rcgr = 0x4054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.hw_clk_ctrl = true,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk3_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk4_clk_src = {
.cmd_rcgr = 0x4070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.hw_clk_ctrl = true,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk4_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk5_clk_src = {
.cmd_rcgr = 0x408c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.hw_clk_ctrl = true,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk5_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk6_clk_src = {
.cmd_rcgr = 0x40a8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.hw_clk_ctrl = true,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk6_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk7_clk_src = {
.cmd_rcgr = 0x40c4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.hw_clk_ctrl = true,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk7_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch cam_bist_mclk_cc_mclk0_clk = {
.halt_reg = 0x4018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk1_clk = {
.halt_reg = 0x4034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk2_clk = {
.halt_reg = 0x4050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk3_clk = {
.halt_reg = 0x406c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x406c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk4_clk = {
.halt_reg = 0x4088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk4_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk5_clk = {
.halt_reg = 0x40a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x40a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk5_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk6_clk = {
.halt_reg = 0x40c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x40c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk6_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk7_clk = {
.halt_reg = 0x40dc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x40dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk7_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *cam_bist_mclk_cc_kaanapali_clocks[] = {
[CAM_BIST_MCLK_CC_MCLK0_CLK] = &cam_bist_mclk_cc_mclk0_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK0_CLK_SRC] = &cam_bist_mclk_cc_mclk0_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK1_CLK] = &cam_bist_mclk_cc_mclk1_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK1_CLK_SRC] = &cam_bist_mclk_cc_mclk1_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK2_CLK] = &cam_bist_mclk_cc_mclk2_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK2_CLK_SRC] = &cam_bist_mclk_cc_mclk2_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK3_CLK] = &cam_bist_mclk_cc_mclk3_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK3_CLK_SRC] = &cam_bist_mclk_cc_mclk3_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK4_CLK] = &cam_bist_mclk_cc_mclk4_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK4_CLK_SRC] = &cam_bist_mclk_cc_mclk4_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK5_CLK] = &cam_bist_mclk_cc_mclk5_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK5_CLK_SRC] = &cam_bist_mclk_cc_mclk5_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK6_CLK] = &cam_bist_mclk_cc_mclk6_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK6_CLK_SRC] = &cam_bist_mclk_cc_mclk6_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK7_CLK] = &cam_bist_mclk_cc_mclk7_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK7_CLK_SRC] = &cam_bist_mclk_cc_mclk7_clk_src.clkr,
[CAM_BIST_MCLK_CC_PLL0] = &cam_bist_mclk_cc_pll0.clkr,
};
static struct clk_alpha_pll *cam_bist_mclk_cc_kaanapali_plls[] = {
&cam_bist_mclk_cc_pll0,
};
static u32 cam_bist_mclk_cc_kaanapali_critical_cbcrs[] = {
0x40e0, /* CAM_BIST_MCLK_CC_SLEEP_CLK */
};
static const struct regmap_config cam_bist_mclk_cc_kaanapali_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x5010,
.fast_io = true,
};
static struct qcom_cc_driver_data cam_bist_mclk_cc_kaanapali_driver_data = {
.alpha_plls = cam_bist_mclk_cc_kaanapali_plls,
.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_plls),
.clk_cbcrs = cam_bist_mclk_cc_kaanapali_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_critical_cbcrs),
};
static const struct qcom_cc_desc cam_bist_mclk_cc_kaanapali_desc = {
.config = &cam_bist_mclk_cc_kaanapali_regmap_config,
.clks = cam_bist_mclk_cc_kaanapali_clocks,
.num_clks = ARRAY_SIZE(cam_bist_mclk_cc_kaanapali_clocks),
.use_rpm = true,
.driver_data = &cam_bist_mclk_cc_kaanapali_driver_data,
};
static const struct of_device_id cam_bist_mclk_cc_kaanapali_match_table[] = {
{ .compatible = "qcom,kaanapali-cambistmclkcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_bist_mclk_cc_kaanapali_match_table);
static int cam_bist_mclk_cc_kaanapali_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &cam_bist_mclk_cc_kaanapali_desc);
}
static struct platform_driver cam_bist_mclk_cc_kaanapali_driver = {
.probe = cam_bist_mclk_cc_kaanapali_probe,
.driver = {
.name = "cambistmclkcc-kaanapali",
.of_match_table = cam_bist_mclk_cc_kaanapali_match_table,
},
};
module_platform_driver(cam_bist_mclk_cc_kaanapali_driver);
MODULE_DESCRIPTION("QTI CAMBISTMCLKCC Kaanapali Driver");
MODULE_LICENSE("GPL");

454
drivers/clk/qcom/cambistmclkcc-sm8750.c Normal file
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@@ -0,0 +1,454 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#include <linux/clk-provider.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <dt-bindings/clock/qcom,sm8750-cambistmclkcc.h>
#include "clk-alpha-pll.h"
#include "clk-branch.h"
#include "clk-rcg.h"
#include "clk-regmap.h"
#include "common.h"
#include "reset.h"
enum {
DT_IFACE,
DT_BI_TCXO,
DT_BI_TCXO_AO,
DT_SLEEP_CLK,
};
enum {
P_BI_TCXO,
P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN,
P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN,
P_SLEEP_CLK,
};
static const struct pll_vco rivian_elu_vco[] = {
{ 833000000, 1125000000, 0 },
{ 777000000, 1062000000, 1 },
};
/* 960.0 MHz Configuration */
static const struct alpha_pll_config cam_bist_mclk_cc_pll0_config = {
.l = 0x32,
.alpha = 0x0,
.config_ctl_val = 0x12000000,
.config_ctl_hi_val = 0x00890263,
.config_ctl_hi1_val = 0x1af04237,
.config_ctl_hi2_val = 0x00000000,
};
static struct clk_alpha_pll cam_bist_mclk_cc_pll0 = {
.offset = 0x0,
.config = &cam_bist_mclk_cc_pll0_config,
.vco_table = rivian_elu_vco,
.num_vco = ARRAY_SIZE(rivian_elu_vco),
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_ELU],
.clkr = {
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_pll0",
.parent_data = &(const struct clk_parent_data) {
.index = DT_BI_TCXO,
},
.num_parents = 1,
.ops = &clk_alpha_pll_rivian_elu_ops,
},
},
};
static const struct parent_map cam_bist_mclk_cc_parent_map_0[] = {
{ P_BI_TCXO, 0 },
{ P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 3 },
{ P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 5 },
};
static const struct clk_parent_data cam_bist_mclk_cc_parent_data_0[] = {
{ .index = DT_BI_TCXO },
{ .hw = &cam_bist_mclk_cc_pll0.clkr.hw },
{ .hw = &cam_bist_mclk_cc_pll0.clkr.hw },
};
static const struct parent_map cam_bist_mclk_cc_parent_map_1[] = {
{ P_SLEEP_CLK, 0 },
};
static const struct clk_parent_data cam_bist_mclk_cc_parent_data_1[] = {
{ .index = DT_SLEEP_CLK },
};
static const struct freq_tbl ftbl_cam_bist_mclk_cc_mclk0_clk_src[] = {
F(12000000, P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 10, 1, 8),
F(19200000, P_BI_TCXO, 1, 0, 0),
F(24000000, P_CAM_BIST_MCLK_CC_PLL0_OUT_EVEN, 10, 1, 4),
F(68571429, P_CAM_BIST_MCLK_CC_PLL0_OUT_MAIN, 14, 0, 0),
{ }
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk0_clk_src = {
.cmd_rcgr = 0x4000,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk0_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk1_clk_src = {
.cmd_rcgr = 0x401c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk1_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk2_clk_src = {
.cmd_rcgr = 0x4038,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk2_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk3_clk_src = {
.cmd_rcgr = 0x4054,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk3_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk4_clk_src = {
.cmd_rcgr = 0x4070,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk4_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk5_clk_src = {
.cmd_rcgr = 0x408c,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk5_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk6_clk_src = {
.cmd_rcgr = 0x40a8,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk6_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_rcg2 cam_bist_mclk_cc_mclk7_clk_src = {
.cmd_rcgr = 0x40c4,
.mnd_width = 8,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_0,
.freq_tbl = ftbl_cam_bist_mclk_cc_mclk0_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk7_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_0,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_0),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static const struct freq_tbl ftbl_cam_bist_mclk_cc_sleep_clk_src[] = {
F(32000, P_SLEEP_CLK, 1, 0, 0),
{ }
};
static struct clk_rcg2 cam_bist_mclk_cc_sleep_clk_src = {
.cmd_rcgr = 0x40e0,
.mnd_width = 0,
.hid_width = 5,
.parent_map = cam_bist_mclk_cc_parent_map_1,
.freq_tbl = ftbl_cam_bist_mclk_cc_sleep_clk_src,
.clkr.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_sleep_clk_src",
.parent_data = cam_bist_mclk_cc_parent_data_1,
.num_parents = ARRAY_SIZE(cam_bist_mclk_cc_parent_data_1),
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_rcg2_shared_ops,
},
};
static struct clk_branch cam_bist_mclk_cc_mclk0_clk = {
.halt_reg = 0x4018,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4018,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk0_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk0_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk1_clk = {
.halt_reg = 0x4034,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4034,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk1_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk1_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk2_clk = {
.halt_reg = 0x4050,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4050,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk2_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk2_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk3_clk = {
.halt_reg = 0x406c,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x406c,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk3_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk3_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk4_clk = {
.halt_reg = 0x4088,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x4088,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk4_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk4_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk5_clk = {
.halt_reg = 0x40a4,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x40a4,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk5_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk5_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk6_clk = {
.halt_reg = 0x40c0,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x40c0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk6_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk6_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_branch cam_bist_mclk_cc_mclk7_clk = {
.halt_reg = 0x40dc,
.halt_check = BRANCH_HALT,
.clkr = {
.enable_reg = 0x40dc,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_bist_mclk_cc_mclk7_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_bist_mclk_cc_mclk7_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};
static struct clk_regmap *cam_bist_mclk_cc_sm8750_clocks[] = {
[CAM_BIST_MCLK_CC_MCLK0_CLK] = &cam_bist_mclk_cc_mclk0_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK0_CLK_SRC] = &cam_bist_mclk_cc_mclk0_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK1_CLK] = &cam_bist_mclk_cc_mclk1_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK1_CLK_SRC] = &cam_bist_mclk_cc_mclk1_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK2_CLK] = &cam_bist_mclk_cc_mclk2_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK2_CLK_SRC] = &cam_bist_mclk_cc_mclk2_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK3_CLK] = &cam_bist_mclk_cc_mclk3_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK3_CLK_SRC] = &cam_bist_mclk_cc_mclk3_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK4_CLK] = &cam_bist_mclk_cc_mclk4_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK4_CLK_SRC] = &cam_bist_mclk_cc_mclk4_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK5_CLK] = &cam_bist_mclk_cc_mclk5_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK5_CLK_SRC] = &cam_bist_mclk_cc_mclk5_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK6_CLK] = &cam_bist_mclk_cc_mclk6_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK6_CLK_SRC] = &cam_bist_mclk_cc_mclk6_clk_src.clkr,
[CAM_BIST_MCLK_CC_MCLK7_CLK] = &cam_bist_mclk_cc_mclk7_clk.clkr,
[CAM_BIST_MCLK_CC_MCLK7_CLK_SRC] = &cam_bist_mclk_cc_mclk7_clk_src.clkr,
[CAM_BIST_MCLK_CC_PLL0] = &cam_bist_mclk_cc_pll0.clkr,
[CAM_BIST_MCLK_CC_SLEEP_CLK_SRC] = &cam_bist_mclk_cc_sleep_clk_src.clkr,
};
static struct clk_alpha_pll *cam_bist_mclk_cc_sm8750_plls[] = {
&cam_bist_mclk_cc_pll0,
};
static u32 cam_bist_mclk_cc_sm8750_critical_cbcrs[] = {
0x40f8, /* CAM_BIST_MCLK_CC_SLEEP_CLK */
};
static const struct regmap_config cam_bist_mclk_cc_sm8750_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.max_register = 0x5010,
.fast_io = true,
};
static struct qcom_cc_driver_data cam_bist_mclk_cc_sm8750_driver_data = {
.alpha_plls = cam_bist_mclk_cc_sm8750_plls,
.num_alpha_plls = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_plls),
.clk_cbcrs = cam_bist_mclk_cc_sm8750_critical_cbcrs,
.num_clk_cbcrs = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_critical_cbcrs),
};
static const struct qcom_cc_desc cam_bist_mclk_cc_sm8750_desc = {
.config = &cam_bist_mclk_cc_sm8750_regmap_config,
.clks = cam_bist_mclk_cc_sm8750_clocks,
.num_clks = ARRAY_SIZE(cam_bist_mclk_cc_sm8750_clocks),
.use_rpm = true,
.driver_data = &cam_bist_mclk_cc_sm8750_driver_data,
};
static const struct of_device_id cam_bist_mclk_cc_sm8750_match_table[] = {
{ .compatible = "qcom,sm8750-cambistmclkcc" },
{ }
};
MODULE_DEVICE_TABLE(of, cam_bist_mclk_cc_sm8750_match_table);
static int cam_bist_mclk_cc_sm8750_probe(struct platform_device *pdev)
{
return qcom_cc_probe(pdev, &cam_bist_mclk_cc_sm8750_desc);
}
static struct platform_driver cam_bist_mclk_cc_sm8750_driver = {
.probe = cam_bist_mclk_cc_sm8750_probe,
.driver = {
.name = "cambistmclkcc-sm8750",
.of_match_table = cam_bist_mclk_cc_sm8750_match_table,
},
};
module_platform_driver(cam_bist_mclk_cc_sm8750_driver);
MODULE_DESCRIPTION("QTI CAMBISTMCLKCC SM8750 Driver");
MODULE_LICENSE("GPL");

2661
drivers/clk/qcom/camcc-kaanapali.c Normal file
View File

File diff suppressed because it is too large Load Diff

2710
drivers/clk/qcom/camcc-sm8750.c Normal file
View File

File diff suppressed because it is too large Load Diff

41
drivers/clk/qcom/clk-alpha-pll.c
View File

@@ -243,6 +243,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL] = 0x28,
[PLL_OFF_TEST_CTL_U] = 0x2c,
},
[CLK_ALPHA_PLL_TYPE_RIVIAN_ELU] = {
[PLL_OFF_OPMODE] = 0x04,
[PLL_OFF_STATUS] = 0x0c,
[PLL_OFF_L_VAL] = 0x10,
[PLL_OFF_USER_CTL] = 0x14,
[PLL_OFF_USER_CTL_U] = 0x18,
[PLL_OFF_CONFIG_CTL] = 0x1c,
[PLL_OFF_CONFIG_CTL_U] = 0x20,
[PLL_OFF_CONFIG_CTL_U1] = 0x24,
[PLL_OFF_CONFIG_CTL_U2] = 0x28,
[PLL_OFF_TEST_CTL] = 0x2c,
[PLL_OFF_TEST_CTL_U] = 0x30,
},
[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
@@ -1257,11 +1270,8 @@ static int clk_alpha_pll_postdiv_determine_rate(struct clk_hw *hw,
else
table = clk_alpha_div_table;
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
table, pll->width,
CLK_DIVIDER_POWER_OF_TWO);
return 0;
return divider_determine_rate(hw, req, table, pll->width,
CLK_DIVIDER_POWER_OF_TWO);
}
static int clk_alpha_pll_postdiv_ro_determine_rate(struct clk_hw *hw,
@@ -1617,11 +1627,8 @@ static int clk_trion_pll_postdiv_determine_rate(struct clk_hw *hw,
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
pll->post_div_table,
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
return 0;
return divider_determine_rate(hw, req, pll->post_div_table, pll->width,
CLK_DIVIDER_ROUND_CLOSEST);
};
static int
@@ -1657,11 +1664,8 @@ static int clk_alpha_pll_postdiv_fabia_determine_rate(struct clk_hw *hw,
{
struct clk_alpha_pll_postdiv *pll = to_clk_alpha_pll_postdiv(hw);
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
pll->post_div_table,
pll->width, CLK_DIVIDER_ROUND_CLOSEST);
return 0;
return divider_determine_rate(hw, req, pll->post_div_table, pll->width,
CLK_DIVIDER_ROUND_CLOSEST);
}
static int clk_alpha_pll_postdiv_fabia_set_rate(struct clk_hw *hw,
@@ -2338,7 +2342,11 @@ void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regma
return;
}
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
if (config->cal_l)
lval |= config->cal_l << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
else
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
@@ -3002,6 +3010,7 @@ void qcom_clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regm
clk_taycan_elu_pll_configure(pll, regmap, pll->config);
break;
case CLK_ALPHA_PLL_TYPE_RIVIAN_EVO:
case CLK_ALPHA_PLL_TYPE_RIVIAN_ELU:
clk_rivian_evo_pll_configure(pll, regmap, pll->config);
break;
case CLK_ALPHA_PLL_TYPE_TRION:

7
drivers/clk/qcom/clk-alpha-pll.h
View File

@@ -28,9 +28,12 @@ enum {
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
CLK_ALPHA_PLL_TYPE_LUCID_OLE,
CLK_ALPHA_PLL_TYPE_PONGO_ELU,
CLK_ALPHA_PLL_TYPE_PONGO_EKO_T = CLK_ALPHA_PLL_TYPE_PONGO_ELU,
CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T = CLK_ALPHA_PLL_TYPE_TAYCAN_ELU,
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
CLK_ALPHA_PLL_TYPE_RIVIAN_ELU,
CLK_ALPHA_PLL_TYPE_RIVIAN_EKO_T = CLK_ALPHA_PLL_TYPE_RIVIAN_ELU,
CLK_ALPHA_PLL_TYPE_DEFAULT_EVO,
CLK_ALPHA_PLL_TYPE_BRAMMO_EVO,
CLK_ALPHA_PLL_TYPE_STROMER,
@@ -128,6 +131,7 @@ struct clk_alpha_pll_postdiv {
struct alpha_pll_config {
u32 l;
u32 cal_l;
u32 alpha;
u32 alpha_hi;
u32 config_ctl_val;
@@ -206,8 +210,11 @@ extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
#define clk_alpha_pll_postdiv_taycan_eko_t_ops clk_alpha_pll_postdiv_lucid_evo_ops
extern const struct clk_ops clk_alpha_pll_pongo_elu_ops;
#define clk_alpha_pll_pongo_eko_t_ops clk_alpha_pll_pongo_elu_ops
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
#define clk_alpha_pll_rivian_elu_ops clk_alpha_pll_rivian_evo_ops
#define clk_alpha_pll_rivian_eko_t_ops clk_alpha_pll_rivian_evo_ops
extern const struct clk_ops clk_alpha_pll_regera_ops;
extern const struct clk_ops clk_alpha_pll_slew_ops;

7
drivers/clk/qcom/clk-rcg2.c
View File

@@ -755,7 +755,7 @@ static int clk_rcg2_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
u32 notn_m, n, m, d, not2d, mask, duty_per, cfg;
u32 notn_m, n, m, d, not2d, mask, cfg;
int ret;
/* Duty-cycle cannot be modified for non-MND RCGs */
@@ -774,10 +774,8 @@ static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
n = (~(notn_m) + m) & mask;
duty_per = (duty->num * 100) / duty->den;
/* Calculate 2d value */
d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100);
d = DIV_ROUND_CLOSEST(n * duty->num * 2, duty->den);
/*
* Check bit widths of 2d. If D is too big reduce duty cycle.
@@ -1266,6 +1264,7 @@ static int clk_gfx3d_determine_rate(struct clk_hw *hw,
if (req->max_rate < parent_req.max_rate)
parent_req.max_rate = req->max_rate;
parent_req.best_parent_hw = req->best_parent_hw;
ret = __clk_determine_rate(req->best_parent_hw, &parent_req);
if (ret)
return ret;

16
drivers/clk/qcom/clk-regmap-divider.c
View File

@@ -26,24 +26,16 @@ static int div_ro_determine_rate(struct clk_hw *hw,
val >>= divider->shift;
val &= BIT(divider->width) - 1;
req->rate = divider_ro_round_rate(hw, req->rate,
&req->best_parent_rate, NULL,
divider->width,
CLK_DIVIDER_ROUND_CLOSEST, val);
return 0;
return divider_ro_determine_rate(hw, req, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST, val);
}
static int div_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
{
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
NULL,
divider->width,
CLK_DIVIDER_ROUND_CLOSEST);
return 0;
return divider_determine_rate(hw, req, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST);
}
static int div_set_rate(struct clk_hw *hw, unsigned long rate,

60
drivers/clk/qcom/clk-rpmh.c
View File

@@ -390,10 +390,21 @@ DEFINE_CLK_RPMH_VRM(clk7, _a4, "clka7", 4);
DEFINE_CLK_RPMH_VRM(div_clk1, _div2, "divclka1", 2);
DEFINE_CLK_RPMH_VRM(clk3, _a, "C3A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk4, _a, "C4A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a, "C5A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk8, _a, "C8A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk1, _a1_e0, "C1A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk2, _a1_e0, "C2A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk3, _a1_e0, "C3A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk4, _a1_e0, "C4A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk5, _a1_e0, "C5A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk8, _a1_e0, "C8A_E0", 1);
DEFINE_CLK_RPMH_VRM(clk3, _a2_e0, "C3A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk4, _a2_e0, "C4A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk5, _a2_e0, "C5A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk6, _a2_e0, "C6A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk7, _a2_e0, "C7A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk8, _a2_e0, "C8A_E0", 2);
DEFINE_CLK_RPMH_VRM(clk11, _a4_e0, "C11A_E0", 4);
DEFINE_CLK_RPMH_BCM(ce, "CE0");
DEFINE_CLK_RPMH_BCM(hwkm, "HK0");
@@ -888,12 +899,12 @@ static const struct clk_rpmh_desc clk_rpmh_sm8750 = {
static struct clk_hw *glymur_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a1_e0.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a1_e0_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a1_e0.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a1_e0_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a1_e0.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a1_e0_ao.hw,
};
static const struct clk_rpmh_desc clk_rpmh_glymur = {
@@ -901,6 +912,34 @@ static const struct clk_rpmh_desc clk_rpmh_glymur = {
.num_clks = ARRAY_SIZE(glymur_rpmh_clocks),
};
static struct clk_hw *kaanapali_rpmh_clocks[] = {
[RPMH_CXO_CLK] = &clk_rpmh_bi_tcxo_div2.hw,
[RPMH_CXO_CLK_A] = &clk_rpmh_bi_tcxo_div2_ao.hw,
[RPMH_DIV_CLK1] = &clk_rpmh_clk11_a4_e0.hw,
[RPMH_LN_BB_CLK1] = &clk_rpmh_clk6_a2_e0.hw,
[RPMH_LN_BB_CLK1_A] = &clk_rpmh_clk6_a2_e0_ao.hw,
[RPMH_LN_BB_CLK2] = &clk_rpmh_clk7_a2_e0.hw,
[RPMH_LN_BB_CLK2_A] = &clk_rpmh_clk7_a2_e0_ao.hw,
[RPMH_LN_BB_CLK3] = &clk_rpmh_clk8_a2_e0.hw,
[RPMH_LN_BB_CLK3_A] = &clk_rpmh_clk8_a2_e0_ao.hw,
[RPMH_RF_CLK1] = &clk_rpmh_clk1_a1_e0.hw,
[RPMH_RF_CLK1_A] = &clk_rpmh_clk1_a1_e0_ao.hw,
[RPMH_RF_CLK2] = &clk_rpmh_clk2_a1_e0.hw,
[RPMH_RF_CLK2_A] = &clk_rpmh_clk2_a1_e0_ao.hw,
[RPMH_RF_CLK3] = &clk_rpmh_clk3_a2_e0.hw,
[RPMH_RF_CLK3_A] = &clk_rpmh_clk3_a2_e0_ao.hw,
[RPMH_RF_CLK4] = &clk_rpmh_clk4_a2_e0.hw,
[RPMH_RF_CLK4_A] = &clk_rpmh_clk4_a2_e0_ao.hw,
[RPMH_RF_CLK5] = &clk_rpmh_clk5_a2_e0.hw,
[RPMH_RF_CLK5_A] = &clk_rpmh_clk5_a2_e0_ao.hw,
[RPMH_IPA_CLK] = &clk_rpmh_ipa.hw,
};
static const struct clk_rpmh_desc clk_rpmh_kaanapali = {
.clks = kaanapali_rpmh_clocks,
.num_clks = ARRAY_SIZE(kaanapali_rpmh_clocks),
};
static struct clk_hw *of_clk_rpmh_hw_get(struct of_phandle_args *clkspec,
void *data)
{
@@ -991,6 +1030,7 @@ static int clk_rpmh_probe(struct platform_device *pdev)
static const struct of_device_id clk_rpmh_match_table[] = {
{ .compatible = "qcom,glymur-rpmh-clk", .data = &clk_rpmh_glymur},
{ .compatible = "qcom,kaanapali-rpmh-clk", .data = &clk_rpmh_kaanapali},
{ .compatible = "qcom,milos-rpmh-clk", .data = &clk_rpmh_milos},
{ .compatible = "qcom,qcs615-rpmh-clk", .data = &clk_rpmh_qcs615},
{ .compatible = "qcom,qdu1000-rpmh-clk", .data = &clk_rpmh_qdu1000},

1956
drivers/clk/qcom/dispcc-kaanapali.c Normal file
View File

File diff suppressed because it is too large Load Diff

4
drivers/clk/qcom/dispcc-sdm845.c
View File

@@ -280,7 +280,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
.name = "disp_cc_mdss_pclk0_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_pixel_ops,
},
};
@@ -295,7 +295,7 @@ static struct clk_rcg2 disp_cc_mdss_pclk1_clk_src = {
.name = "disp_cc_mdss_pclk1_clk_src",
.parent_data = disp_cc_parent_data_4,
.num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_pixel_ops,
},
};

2
drivers/clk/qcom/dispcc-sm7150.c
View File

@@ -371,7 +371,7 @@ static struct clk_rcg2 dispcc_mdss_pclk1_clk_src = {
.name = "dispcc_mdss_pclk1_clk_src",
.parent_data = dispcc_parent_data_4,
.num_parents = ARRAY_SIZE(dispcc_parent_data_4),
.flags = CLK_SET_RATE_PARENT,
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
.ops = &clk_pixel_ops,
},
};

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