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https://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf.git
synced 2026-04-04 15:58:25 -04:00
power: supply: bd71828-power: Support ROHM BD72720
The ROHM BD72720 is a power management IC with a charger and coulomb counter block which is closely related to the charger / coulomb counter found from the BD71815, BD71828, BD71879 which are all supported by the bd71828-power driver. Due to the similarities it makes sense to support also the BD72720 with the same driver. Add basic support for the charger logic on ROHM BD72720. Signed-off-by: Matti Vaittinen <mazziesaccount@gmail.com> Link: https://patch.msgid.link/fb74c0cab3dfe534135d26dbbb9c66699678c2de.1765804226.git.mazziesaccount@gmail.com Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
Matti Vaittinen
committed by
Lee Jones
Lee Jones
parent
de8f20afb0
commit
bcb5bb59b8
@@ -5,6 +5,7 @@
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#include <linux/kernel.h>
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#include <linux/mfd/rohm-bd71815.h>
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#include <linux/mfd/rohm-bd71828.h>
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#include <linux/mfd/rohm-bd72720.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/platform_device.h>
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@@ -51,12 +52,14 @@ struct pwr_regs {
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unsigned int chg_state;
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unsigned int bat_temp;
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unsigned int dcin_stat;
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unsigned int dcin_online_mask;
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unsigned int dcin_collapse_limit;
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unsigned int chg_set1;
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unsigned int chg_en;
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unsigned int vbat_alm_limit_u;
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unsigned int conf;
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unsigned int vdcin;
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unsigned int vdcin_himask;
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};
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static const struct pwr_regs pwr_regs_bd71828 = {
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@@ -67,12 +70,14 @@ static const struct pwr_regs pwr_regs_bd71828 = {
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.chg_state = BD71828_REG_CHG_STATE,
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.bat_temp = BD71828_REG_BAT_TEMP,
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.dcin_stat = BD71828_REG_DCIN_STAT,
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.dcin_online_mask = BD7182x_MASK_DCIN_DET,
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.dcin_collapse_limit = BD71828_REG_DCIN_CLPS,
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.chg_set1 = BD71828_REG_CHG_SET1,
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.chg_en = BD71828_REG_CHG_EN,
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.vbat_alm_limit_u = BD71828_REG_ALM_VBAT_LIMIT_U,
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.conf = BD71828_REG_CONF,
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.vdcin = BD71828_REG_VDCIN_U,
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.vdcin_himask = BD7182x_MASK_VDCIN_U,
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};
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static const struct pwr_regs pwr_regs_bd71815 = {
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@@ -85,6 +90,7 @@ static const struct pwr_regs pwr_regs_bd71815 = {
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.chg_state = BD71815_REG_CHG_STATE,
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.bat_temp = BD71815_REG_BAT_TEMP,
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.dcin_stat = BD71815_REG_DCIN_STAT,
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.dcin_online_mask = BD7182x_MASK_DCIN_DET,
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.dcin_collapse_limit = BD71815_REG_DCIN_CLPS,
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.chg_set1 = BD71815_REG_CHG_SET1,
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.chg_en = BD71815_REG_CHG_SET1,
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@@ -92,6 +98,31 @@ static const struct pwr_regs pwr_regs_bd71815 = {
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.conf = BD71815_REG_CONF,
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.vdcin = BD71815_REG_VM_DCIN_U,
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.vdcin_himask = BD7182x_MASK_VDCIN_U,
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};
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static struct pwr_regs pwr_regs_bd72720 = {
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.vbat_avg = BD72720_REG_VM_SA_VBAT_U,
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.ibat = BD72720_REG_CC_CURCD_U,
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.ibat_avg = BD72720_REG_CC_SA_CURCD_U,
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.btemp_vth = BD72720_REG_VM_BTMP_U,
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/*
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* Note, state 0x40 IMP_CHK. not documented
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* on other variants but was still handled in
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* existing code. No memory traces as to why.
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*/
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.chg_state = BD72720_REG_CHG_STATE,
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.bat_temp = BD72720_REG_CHG_BAT_TEMP_STAT,
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.dcin_stat = BD72720_REG_INT_VBUS_SRC,
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.dcin_online_mask = BD72720_MASK_DCIN_DET,
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.dcin_collapse_limit = -1, /* Automatic. Setting not supported */
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.chg_set1 = BD72720_REG_CHG_SET_1,
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.chg_en = BD72720_REG_CHG_EN,
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/* 15mV note in data-sheet */
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.vbat_alm_limit_u = BD72720_REG_ALM_VBAT_TH_U,
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.conf = BD72720_REG_CONF, /* o XSTB, only PON. Seprate slave addr */
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.vdcin = BD72720_REG_VM_VBUS_U, /* 10 bits not 11 as with other ICs */
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.vdcin_himask = BD72720_MASK_VDCIN_U,
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};
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struct bd71828_power {
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@@ -298,7 +329,7 @@ static int get_chg_online(struct bd71828_power *pwr, int *chg_online)
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dev_err(pwr->dev, "Failed to read DCIN status\n");
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return ret;
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}
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*chg_online = ((r & BD7182x_MASK_DCIN_DET) != 0);
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*chg_online = ((r & pwr->regs->dcin_online_mask) != 0);
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return 0;
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}
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@@ -329,8 +360,8 @@ static int bd71828_bat_inserted(struct bd71828_power *pwr)
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ret = val & BD7182x_MASK_CONF_PON;
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if (ret)
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regmap_update_bits(pwr->regmap, pwr->regs->conf,
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BD7182x_MASK_CONF_PON, 0);
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if (regmap_update_bits(pwr->regmap, pwr->regs->conf, BD7182x_MASK_CONF_PON, 0))
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dev_err(pwr->dev, "Failed to write CONF register\n");
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return ret;
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}
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@@ -358,11 +389,13 @@ static int bd71828_init_hardware(struct bd71828_power *pwr)
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int ret;
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/* TODO: Collapse limit should come from device-tree ? */
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ret = regmap_write(pwr->regmap, pwr->regs->dcin_collapse_limit,
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BD7182x_DCIN_COLLAPSE_DEFAULT);
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if (ret) {
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dev_err(pwr->dev, "Failed to write DCIN collapse limit\n");
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return ret;
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if (pwr->regs->dcin_collapse_limit != (unsigned int)-1) {
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ret = regmap_write(pwr->regmap, pwr->regs->dcin_collapse_limit,
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BD7182x_DCIN_COLLAPSE_DEFAULT);
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if (ret) {
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dev_err(pwr->dev, "Failed to write DCIN collapse limit\n");
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return ret;
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}
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}
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ret = pwr->bat_inserted(pwr);
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@@ -419,7 +452,7 @@ static int bd71828_charger_get_property(struct power_supply *psy,
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break;
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case POWER_SUPPLY_PROP_VOLTAGE_NOW:
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ret = bd7182x_read16_himask(pwr, pwr->regs->vdcin,
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BD7182x_MASK_VDCIN_U, &tmp);
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pwr->regs->vdcin_himask, &tmp);
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if (ret)
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return ret;
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@@ -630,6 +663,9 @@ BD_ISR_AC(dcin_ovp_det, "DCIN OVER VOLTAGE", true)
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BD_ISR_DUMMY(dcin_mon_det, "DCIN voltage below threshold")
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BD_ISR_DUMMY(dcin_mon_res, "DCIN voltage above threshold")
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BD_ISR_DUMMY(vbus_curr_limit, "VBUS current limited")
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BD_ISR_DUMMY(vsys_ov_res, "VSYS over-voltage cleared")
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BD_ISR_DUMMY(vsys_ov_det, "VSYS over-voltage")
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BD_ISR_DUMMY(vsys_uv_res, "VSYS under-voltage cleared")
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BD_ISR_DUMMY(vsys_uv_det, "VSYS under-voltage")
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BD_ISR_DUMMY(vsys_low_res, "'VSYS low' cleared")
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@@ -878,6 +914,51 @@ static int bd7182x_get_irqs(struct platform_device *pdev,
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BDIRQ("bd71828-temp-125-over", bd71828_temp_vf125_det),
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BDIRQ("bd71828-temp-125-under", bd71828_temp_vf125_res),
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};
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static const struct bd7182x_irq_res bd72720_irqs[] = {
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BDIRQ("bd72720_int_vbus_rmv", BD_ISR_NAME(dcin_removed)),
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BDIRQ("bd72720_int_vbus_det", bd7182x_dcin_detected),
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BDIRQ("bd72720_int_vbus_mon_res", BD_ISR_NAME(dcin_mon_res)),
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BDIRQ("bd72720_int_vbus_mon_det", BD_ISR_NAME(dcin_mon_det)),
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BDIRQ("bd72720_int_vsys_mon_res", BD_ISR_NAME(vsys_mon_res)),
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BDIRQ("bd72720_int_vsys_mon_det", BD_ISR_NAME(vsys_mon_det)),
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BDIRQ("bd72720_int_vsys_uv_res", BD_ISR_NAME(vsys_uv_res)),
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BDIRQ("bd72720_int_vsys_uv_det", BD_ISR_NAME(vsys_uv_det)),
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BDIRQ("bd72720_int_vsys_lo_res", BD_ISR_NAME(vsys_low_res)),
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BDIRQ("bd72720_int_vsys_lo_det", BD_ISR_NAME(vsys_low_det)),
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BDIRQ("bd72720_int_vsys_ov_res", BD_ISR_NAME(vsys_ov_res)),
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BDIRQ("bd72720_int_vsys_ov_det", BD_ISR_NAME(vsys_ov_det)),
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BDIRQ("bd72720_int_bat_ilim", BD_ISR_NAME(vbus_curr_limit)),
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BDIRQ("bd72720_int_chg_done", bd718x7_chg_done),
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BDIRQ("bd72720_int_extemp_tout", BD_ISR_NAME(chg_wdg_temp)),
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BDIRQ("bd72720_int_chg_wdt_exp", BD_ISR_NAME(chg_wdg)),
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BDIRQ("bd72720_int_bat_mnt_out", BD_ISR_NAME(rechg_res)),
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BDIRQ("bd72720_int_bat_mnt_in", BD_ISR_NAME(rechg_det)),
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BDIRQ("bd72720_int_chg_trns", BD_ISR_NAME(chg_state_changed)),
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BDIRQ("bd72720_int_vbat_mon_res", BD_ISR_NAME(bat_mon_res)),
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BDIRQ("bd72720_int_vbat_mon_det", BD_ISR_NAME(bat_mon)),
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BDIRQ("bd72720_int_vbat_sht_res", BD_ISR_NAME(bat_short_res)),
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BDIRQ("bd72720_int_vbat_sht_det", BD_ISR_NAME(bat_short)),
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BDIRQ("bd72720_int_vbat_lo_res", BD_ISR_NAME(bat_low_res)),
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BDIRQ("bd72720_int_vbat_lo_det", BD_ISR_NAME(bat_low)),
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BDIRQ("bd72720_int_vbat_ov_res", BD_ISR_NAME(bat_ov_res)),
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BDIRQ("bd72720_int_vbat_ov_det", BD_ISR_NAME(bat_ov)),
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BDIRQ("bd72720_int_bat_rmv", BD_ISR_NAME(bat_removed)),
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BDIRQ("bd72720_int_bat_det", BD_ISR_NAME(bat_det)),
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BDIRQ("bd72720_int_dbat_det", BD_ISR_NAME(bat_dead)),
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BDIRQ("bd72720_int_bat_temp_trns", BD_ISR_NAME(temp_transit)),
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BDIRQ("bd72720_int_lobtmp_res", BD_ISR_NAME(temp_bat_low_res)),
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BDIRQ("bd72720_int_lobtmp_det", BD_ISR_NAME(temp_bat_low)),
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BDIRQ("bd72720_int_ovbtmp_res", BD_ISR_NAME(temp_bat_hi_res)),
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BDIRQ("bd72720_int_ovbtmp_det", BD_ISR_NAME(temp_bat_hi)),
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BDIRQ("bd72720_int_ocur1_res", BD_ISR_NAME(bat_oc1_res)),
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BDIRQ("bd72720_int_ocur1_det", BD_ISR_NAME(bat_oc1)),
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BDIRQ("bd72720_int_ocur2_res", BD_ISR_NAME(bat_oc2_res)),
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BDIRQ("bd72720_int_ocur2_det", BD_ISR_NAME(bat_oc2)),
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BDIRQ("bd72720_int_ocur3_res", BD_ISR_NAME(bat_oc3_res)),
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BDIRQ("bd72720_int_ocur3_det", BD_ISR_NAME(bat_oc3)),
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BDIRQ("bd72720_int_cc_mon2_det", BD_ISR_NAME(bat_cc_mon)),
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};
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int num_irqs;
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const struct bd7182x_irq_res *irqs;
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@@ -890,6 +971,10 @@ static int bd7182x_get_irqs(struct platform_device *pdev,
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irqs = &bd71815_irqs[0];
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num_irqs = ARRAY_SIZE(bd71815_irqs);
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break;
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case ROHM_CHIP_TYPE_BD72720:
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irqs = &bd72720_irqs[0];
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num_irqs = ARRAY_SIZE(bd72720_irqs);
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break;
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default:
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return -EINVAL;
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}
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@@ -958,21 +1043,27 @@ static int bd71828_power_probe(struct platform_device *pdev)
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struct power_supply_config ac_cfg = {};
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struct power_supply_config bat_cfg = {};
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int ret;
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struct regmap *regmap;
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regmap = dev_get_regmap(pdev->dev.parent, NULL);
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if (!regmap) {
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dev_err(&pdev->dev, "No parent regmap\n");
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return -EINVAL;
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}
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pwr = devm_kzalloc(&pdev->dev, sizeof(*pwr), GFP_KERNEL);
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if (!pwr)
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return -ENOMEM;
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pwr->regmap = regmap;
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pwr->dev = &pdev->dev;
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/*
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* The BD72720 MFD device registers two regmaps. Power-supply driver
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* uses the "wrap-map", which provides access to both of the I2C slave
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* addresses used by the BD72720
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*/
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pwr->chip_type = platform_get_device_id(pdev)->driver_data;
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if (pwr->chip_type != ROHM_CHIP_TYPE_BD72720)
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pwr->regmap = dev_get_regmap(pdev->dev.parent, NULL);
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else
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pwr->regmap = dev_get_regmap(pdev->dev.parent, "wrap-map");
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if (!pwr->regmap) {
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dev_err(&pdev->dev, "No parent regmap\n");
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return -EINVAL;
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}
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pwr->dev = &pdev->dev;
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switch (pwr->chip_type) {
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case ROHM_CHIP_TYPE_BD71828:
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@@ -985,6 +1076,12 @@ static int bd71828_power_probe(struct platform_device *pdev)
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pwr->get_temp = bd71815_get_temp;
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pwr->regs = &pwr_regs_bd71815;
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break;
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case ROHM_CHIP_TYPE_BD72720:
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pwr->bat_inserted = bd71828_bat_inserted;
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pwr->regs = &pwr_regs_bd72720;
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pwr->get_temp = bd71828_get_temp;
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dev_dbg(pwr->dev, "Found ROHM BD72720\n");
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break;
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default:
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dev_err(pwr->dev, "Unknown PMIC\n");
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return -EINVAL;
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@@ -1030,6 +1127,7 @@ static int bd71828_power_probe(struct platform_device *pdev)
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static const struct platform_device_id bd71828_charger_id[] = {
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{ "bd71815-power", ROHM_CHIP_TYPE_BD71815 },
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{ "bd71828-power", ROHM_CHIP_TYPE_BD71828 },
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{ "bd72720-power", ROHM_CHIP_TYPE_BD72720 },
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{ },
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};
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MODULE_DEVICE_TABLE(platform, bd71828_charger_id);
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