Commit 08a7d252 authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

tools arch x86: Sync the msr-index.h copy with the kernel sources 

To pick up the changes from these csets:

  dc1e67f7 ("KVM VMX: Move MSR_IA32_VMX_MISC bit defines to asm/vmx.h")
  d7bfc9ff ("KVM: VMX: Move MSR_IA32_VMX_BASIC bit defines to asm/vmx.h")
  beb2e446 ("x86/cpu: KVM: Move macro to encode PAT value to common header")
  e7e80b66 ("x86/cpu: KVM: Add common defines for architectural memory types (PAT, MTRRs, etc.)")

That cause no changes to tooling:

  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after
  $ diff -u before after
  $

To see how this works take a look at this previous update:

  https://git.kernel.org/torvalds/c/174372668933ede5

  17437266 ("tools arch x86: Sync the msr-index.h copy with the kernel sources to pick IA32_MKTME_KEYID_PARTITIONING")

Just silences this perf build warning:

  Warning: Kernel ABI header differences:
    diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Please see tools/include/uapi/README for further details.

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Xin Li <xin3.li@intel.com>
Link: https://lore.kernel.org/lkml/ZxpLSBzGin3vjs3b@x1


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 758f1815

tools/arch/x86/include/asm/msr-index.h

+20 −14
Original line number Diff line number Diff line
@@ -36,6 +36,20 @@ 
#define EFER_FFXSR		(1<<_EFER_FFXSR)

#define EFER_AUTOIBRS		(1<<_EFER_AUTOIBRS)



/*

 * Architectural memory types that are common to MTRRs, PAT, VMX MSRs, etc.

 * Most MSRs support/allow only a subset of memory types, but the values

 * themselves are common across all relevant MSRs.

 */

#define X86_MEMTYPE_UC		0ull	/* Uncacheable, a.k.a. Strong Uncacheable */

#define X86_MEMTYPE_WC		1ull	/* Write Combining */

/* RESERVED			2 */

/* RESERVED			3 */

#define X86_MEMTYPE_WT		4ull	/* Write Through */

#define X86_MEMTYPE_WP		5ull	/* Write Protected */

#define X86_MEMTYPE_WB		6ull	/* Write Back */

#define X86_MEMTYPE_UC_MINUS	7ull	/* Weak Uncacheabled (PAT only) */



/* FRED MSRs */

#define MSR_IA32_FRED_RSP0	0x1cc			/* Level 0 stack pointer */

#define MSR_IA32_FRED_RSP1	0x1cd			/* Level 1 stack pointer */
@@ -365,6 +379,12 @@ 


#define MSR_IA32_CR_PAT			0x00000277



#define PAT_VALUE(p0, p1, p2, p3, p4, p5, p6, p7)			\

	((X86_MEMTYPE_ ## p0)      | (X86_MEMTYPE_ ## p1 << 8)  |	\

	(X86_MEMTYPE_ ## p2 << 16) | (X86_MEMTYPE_ ## p3 << 24) |	\

	(X86_MEMTYPE_ ## p4 << 32) | (X86_MEMTYPE_ ## p5 << 40) |	\

	(X86_MEMTYPE_ ## p6 << 48) | (X86_MEMTYPE_ ## p7 << 56))



#define MSR_IA32_DEBUGCTLMSR		0x000001d9

#define MSR_IA32_LASTBRANCHFROMIP	0x000001db

#define MSR_IA32_LASTBRANCHTOIP		0x000001dc
@@ -1159,15 +1179,6 @@ 
#define MSR_IA32_VMX_VMFUNC             0x00000491

#define MSR_IA32_VMX_PROCBASED_CTLS3	0x00000492



/* VMX_BASIC bits and bitmasks */

#define VMX_BASIC_VMCS_SIZE_SHIFT	32

#define VMX_BASIC_TRUE_CTLS		(1ULL << 55)

#define VMX_BASIC_64		0x0001000000000000LLU

#define VMX_BASIC_MEM_TYPE_SHIFT	50

#define VMX_BASIC_MEM_TYPE_MASK	0x003c000000000000LLU

#define VMX_BASIC_MEM_TYPE_WB	6LLU

#define VMX_BASIC_INOUT		0x0040000000000000LLU



/* Resctrl MSRs: */

/* - Intel: */

#define MSR_IA32_L3_QOS_CFG		0xc81
@@ -1185,11 +1196,6 @@ 
#define MSR_IA32_SMBA_BW_BASE		0xc0000280

#define MSR_IA32_EVT_CFG_BASE		0xc0000400



/* MSR_IA32_VMX_MISC bits */

#define MSR_IA32_VMX_MISC_INTEL_PT                 (1ULL << 14)

#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29)

#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE   0x1F



/* AMD-V MSRs */

#define MSR_VM_CR                       0xc0010114

#define MSR_VM_IGNNE                    0xc0010115