Commit 1d2da923 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-airoha', 'clk-rockchip', 'clk-stm', 'clk-thead' and 'clk-bcm' into clk-next

* clk-airoha:
  clk: en7523: Add clock for eMMC for EN7581
  dt-bindings: clock: add ID for eMMC for EN7581
  dt-bindings: clock: drop NUM_CLOCKS define for EN7581
  clk: en7523: Rework clock handling for different clock numbers
  clk: en7523: Initialize num before accessing hws in en7523_register_clocks()
  clk: en7523: Fix wrong BUS clock for EN7581
  clk: amlogic: axg-audio: revert reset implementation
  Revert "clk: Fix invalid execution of clk_set_rate"

* clk-rockchip:
  clk: rockchip: rk3588: make refclko25m_ethX critical
  clk: rockchip: rk3588: drop RK3588_LINKED_CLK
  clk: rockchip: implement linked gate clock support
  clk: rockchip: expose rockchip_clk_set_lookup
  clk: rockchip: rk3588: register GATE_LINK later
  clk: rockchip: support clocks registered late

* clk-stm:
  clk: stm32f4: support spread spectrum clock generation
  clk: stm32f4: use FIELD helpers to access the PLLCFGR fields
  dt-bindings: clock: st,stm32-rcc: support spread spectrum clocking
  dt-bindings: clock: convert stm32 rcc bindings to json-schema

* clk-thead:
  clk: thead: Fix cpu2vp_clk for TH1520 AP_SUBSYS clocks
  clk: thead: Add CLK_IGNORE_UNUSED to fix TH1520 boot
  clk: thead: Fix clk gate registration to pass flags

* clk-bcm:
  clk: bcm: rpi: Add disp clock
  clk: bcm: rpi: Create helper to retrieve private data
  clk: bcm: rpi: Enable minimize for all firmware clocks
  clk: bcm: rpi: Allow cpufreq driver to also adjust gpu clocks
  clk: bcm: rpi: Add ISP to exported clocks
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+0 −138
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STMicroelectronics STM32 Reset and Clock Controller
===================================================

The RCC IP is both a reset and a clock controller.

Please refer to clock-bindings.txt for common clock controller binding usage.
Please also refer to reset.txt for common reset controller binding usage.

Required properties:
- compatible: Should be:
  "st,stm32f42xx-rcc"
  "st,stm32f469-rcc"
  "st,stm32f746-rcc"
  "st,stm32f769-rcc"

- reg: should be register base and length as documented in the
  datasheet
- #reset-cells: 1, see below
- #clock-cells: 2, device nodes should specify the clock in their "clocks"
  property, containing a phandle to the clock device node, an index selecting
  between gated clocks and other clocks and an index specifying the clock to
  use.
- clocks: External oscillator clock phandle
  - high speed external clock signal (HSE)
  - external I2S clock (I2S_CKIN)

Example:

	rcc: rcc@40023800 {
		#reset-cells = <1>;
		#clock-cells = <2>
		compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
		reg = <0x40023800 0x400>;
		clocks = <&clk_hse>, <&clk_i2s_ckin>;
	};

Specifying gated clocks
=======================

The primary index must be set to 0.

The secondary index is the bit number within the RCC register bank, starting
from the first RCC clock enable register (RCC_AHB1ENR, address offset 0x30).

It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register (LSB is 0, MSB is 31).

To simplify the usage and to share bit definition with the reset and clock
drivers of the RCC IP, macros are available to generate the index in
human-readble format.

For STM32F4 series, the macro are available here:
 - include/dt-bindings/mfd/stm32f4-rcc.h

Example:

	/* Gated clock, AHB1 bit 0 (GPIOA) */
	... {
		clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
	};

	/* Gated clock, AHB2 bit 4 (CRYP) */
	... {
		clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
	};

Specifying other clocks
=======================

The primary index must be set to 1.

The secondary index is bound with the following magic numbers:

	0	SYSTICK
	1	FCLK
	2	CLK_LSI		(low-power clock source)
	3	CLK_LSE		(generated from a 32.768 kHz low-speed external
				 crystal or ceramic resonator)
	4	CLK_HSE_RTC	(HSE division factor for RTC clock)
	5	CLK_RTC		(real-time clock)
	6	PLL_VCO_I2S	(vco frequency of I2S pll)
	7	PLL_VCO_SAI	(vco frequency of SAI pll)
	8	CLK_LCD		(LCD-TFT)
	9	CLK_I2S		(I2S clocks)
	10	CLK_SAI1	(audio clocks)
	11	CLK_SAI2
	12	CLK_I2SQ_PDIV	(post divisor of pll i2s q divisor)
	13	CLK_SAIQ_PDIV	(post divisor of pll sai q divisor)

	14	CLK_HSI		(Internal ocscillator clock)
	15	CLK_SYSCLK	(System Clock)
	16	CLK_HDMI_CEC	(HDMI-CEC clock)
	17	CLK_SPDIF	(SPDIF-Rx clock)
	18	CLK_USART1	(U(s)arts clocks)
	19	CLK_USART2
	20	CLK_USART3
	21	CLK_UART4
	22	CLK_UART5
	23	CLK_USART6
	24	CLK_UART7
	25	CLK_UART8
	26	CLK_I2C1	(I2S clocks)
	27	CLK_I2C2
	28	CLK_I2C3
	29	CLK_I2C4
	30	CLK_LPTIMER	(LPTimer1 clock)
	31	CLK_PLL_SRC
	32	CLK_DFSDM1
	33	CLK_ADFSDM1
	34	CLK_F769_DSI
)

Example:

	/* Misc clock, FCLK */
	... {
		clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
	};


Specifying softreset control of devices
=======================================

Device nodes should specify the reset channel required in their "resets"
property, containing a phandle to the reset device node and an index specifying
which channel to use.
The index is the bit number within the RCC registers bank, starting from RCC
base address.
It is calculated as: index = register_offset / 4 * 32 + bit_offset.
Where bit_offset is the bit offset within the register.
For example, for CRC reset:
  crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140

example:

	timer2 {
		resets	= <&rcc STM32F4_APB1_RESET(TIM2)>;
	};
+144 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/st,stm32-rcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 Reset Clock Controller

maintainers:
  - Dario Binacchi <dario.binacchi@amarulasolutions.com>

description: |
  The RCC IP is both a reset and a clock controller.
  The reset phandle argument is the bit number within the RCC registers bank,
  starting from RCC base address.

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - st,stm32f42xx-rcc
              - st,stm32f746-rcc
              - st,stm32h743-rcc
          - const: st,stm32-rcc
      - items:
          - enum:
              - st,stm32f469-rcc
          - const: st,stm32f42xx-rcc
          - const: st,stm32-rcc
      - items:
          - enum:
              - st,stm32f769-rcc
          - const: st,stm32f746-rcc
          - const: st,stm32-rcc

  reg:
    maxItems: 1

  '#reset-cells':
    const: 1

  '#clock-cells':
    enum: [1, 2]

  clocks:
    minItems: 2
    maxItems: 3

  st,syscfg:
    $ref: /schemas/types.yaml#/definitions/phandle
    description:
      Phandle to system configuration controller. It can be used to control the
      power domain circuitry.

  st,ssc-modfreq-hz:
    description:
      The modulation frequency for main PLL (in Hz)

  st,ssc-moddepth-permyriad:
    $ref: /schemas/types.yaml#/definitions/uint32
    description:
      The modulation rate for main PLL (in permyriad, i.e. 0.01%)
    minimum: 25
    maximum: 200

  st,ssc-modmethod:
    $ref: /schemas/types.yaml#/definitions/string
    description:
      The modulation techniques for main PLL.
    items:
      enum:
        - center-spread
        - down-spread

required:
  - compatible
  - reg
  - '#reset-cells'
  - '#clock-cells'
  - clocks
  - st,syscfg

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: st,stm32h743-rcc
    then:
      properties:
        '#clock-cells':
          const: 1
          description: |
            The clock index for the specified type.
        clocks:
          items:
            - description: high speed external (HSE) clock input
            - description: low speed external (LSE) clock input
            - description: Inter-IC sound (I2S) clock input
        st,ssc-modfreq-hz: false
        st,ssc-moddepth-permyriad: false
        st,ssc-modmethod: false

    else:
      properties:
        '#clock-cells':
          const: 2
          description: |
            - The first cell is the clock type, possible values are 0 for
              gated clocks and 1 otherwise.
            - The second cell is the clock index for the specified type.
        clocks:
          items:
            - description: high speed external (HSE) clock input
            - description: Inter-IC sound (I2S) clock input

additionalProperties: false

examples:
  # Reset and Clock Control Module node:
  - |
    clock-controller@40023800 {
        compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
        reg = <0x40023800 0x400>;
        #clock-cells = <2>;
        #reset-cells = <1>;
        clocks = <&clk_hse>, <&clk_i2s_ckin>;
        st,syscfg = <&pwrcfg>;
        st,ssc-modfreq-hz = <10000>;
        st,ssc-moddepth-permyriad = <200>;
        st,ssc-modmethod = "center-spread";
    };
  - |
    clock-controller@58024400 {
        compatible = "st,stm32h743-rcc", "st,stm32-rcc";
        reg = <0x58024400 0x400>;
        #clock-cells = <1>;
        #reset-cells = <1>;
        clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
        st,syscfg = <&pwrcfg>;
    };

...
+1 −1
Original line number Diff line number Diff line
@@ -3,4 +3,4 @@ STMicroelectronics STM32 Peripheral Reset Controller

The RCC IP is both a reset and a clock controller.

Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
+24 −9
Original line number Diff line number Diff line
@@ -34,6 +34,7 @@ static char *rpi_firmware_clk_names[] = {
	[RPI_FIRMWARE_M2MC_CLK_ID]	= "m2mc",
	[RPI_FIRMWARE_PIXEL_BVB_CLK_ID]	= "pixel-bvb",
	[RPI_FIRMWARE_VEC_CLK_ID]	= "vec",
	[RPI_FIRMWARE_DISP_CLK_ID]	= "disp",
};

#define RPI_FIRMWARE_STATE_ENABLE_BIT	BIT(0)
@@ -56,6 +57,12 @@ struct raspberrypi_clk_data {
	struct raspberrypi_clk *rpi;
};

static inline
const struct raspberrypi_clk_data *clk_hw_to_data(const struct clk_hw *hw)
{
	return container_of(hw, struct raspberrypi_clk_data, hw);
}

struct raspberrypi_clk_variant {
	bool		export;
	char		*clkdev;
@@ -111,18 +118,31 @@ raspberrypi_clk_variants[RPI_FIRMWARE_NUM_CLK_ID] = {
	},
	[RPI_FIRMWARE_V3D_CLK_ID] = {
		.export = true,
		.minimize = true,
	},
	[RPI_FIRMWARE_PIXEL_CLK_ID] = {
		.export = true,
		.minimize = true,
	},
	[RPI_FIRMWARE_HEVC_CLK_ID] = {
		.export = true,
		.minimize = true,
	},
	[RPI_FIRMWARE_ISP_CLK_ID] = {
		.export = true,
		.minimize = true,
	},
	[RPI_FIRMWARE_PIXEL_BVB_CLK_ID] = {
		.export = true,
		.minimize = true,
	},
	[RPI_FIRMWARE_VEC_CLK_ID] = {
		.export = true,
		.minimize = true,
	},
	[RPI_FIRMWARE_DISP_CLK_ID] = {
		.export = true,
		.minimize = true,
	},
};

@@ -153,7 +173,6 @@ static int raspberrypi_clock_property(struct rpi_firmware *firmware,
	struct raspberrypi_firmware_prop msg = {
		.id = cpu_to_le32(data->id),
		.val = cpu_to_le32(*val),
		.disable_turbo = cpu_to_le32(1),
	};
	int ret;

@@ -168,8 +187,7 @@ static int raspberrypi_clock_property(struct rpi_firmware *firmware,

static int raspberrypi_fw_is_prepared(struct clk_hw *hw)
{
	struct raspberrypi_clk_data *data =
		container_of(hw, struct raspberrypi_clk_data, hw);
	const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
	struct raspberrypi_clk *rpi = data->rpi;
	u32 val = 0;
	int ret;
@@ -186,8 +204,7 @@ static int raspberrypi_fw_is_prepared(struct clk_hw *hw)
static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,
					     unsigned long parent_rate)
{
	struct raspberrypi_clk_data *data =
		container_of(hw, struct raspberrypi_clk_data, hw);
	const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
	struct raspberrypi_clk *rpi = data->rpi;
	u32 val = 0;
	int ret;
@@ -203,8 +220,7 @@ static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,
static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
				   unsigned long parent_rate)
{
	struct raspberrypi_clk_data *data =
		container_of(hw, struct raspberrypi_clk_data, hw);
	const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
	struct raspberrypi_clk *rpi = data->rpi;
	u32 _rate = rate;
	int ret;
@@ -221,8 +237,7 @@ static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
static int raspberrypi_fw_dumb_determine_rate(struct clk_hw *hw,
					      struct clk_rate_request *req)
{
	struct raspberrypi_clk_data *data =
		container_of(hw, struct raspberrypi_clk_data, hw);
	const struct raspberrypi_clk_data *data = clk_hw_to_data(hw);
	struct raspberrypi_clk_variant *variant = data->variant;

	/*
+21 −8
Original line number Diff line number Diff line
@@ -75,6 +75,7 @@ struct en_rst_data {
};

struct en_clk_soc_data {
	u32 num_clocks;
	const struct clk_ops pcie_ops;
	int (*hw_init)(struct platform_device *pdev,
		       struct clk_hw_onecell_data *clk_data);
@@ -87,8 +88,10 @@ static const u32 slic_base[] = { 100000000, 3125000 };
static const u32 npu_base[] = { 333000000, 400000000, 500000000 };
/* EN7581 */
static const u32 emi7581_base[] = { 540000000, 480000000, 400000000, 300000000 };
static const u32 bus7581_base[] = { 600000000, 540000000 };
static const u32 npu7581_base[] = { 800000000, 750000000, 720000000, 600000000 };
static const u32 crypto_base[] = { 540000000, 480000000 };
static const u32 emmc7581_base[] = { 200000000, 150000000 };

static const struct en_clk_desc en7523_base_clks[] = {
	{
@@ -222,8 +225,8 @@ static const struct en_clk_desc en7581_base_clks[] = {
		.base_reg = REG_BUS_CLK_DIV_SEL,
		.base_bits = 1,
		.base_shift = 8,
		.base_values = bus_base,
		.n_base_values = ARRAY_SIZE(bus_base),
		.base_values = bus7581_base,
		.n_base_values = ARRAY_SIZE(bus7581_base),

		.div_bits = 3,
		.div_shift = 0,
@@ -279,6 +282,15 @@ static const struct en_clk_desc en7581_base_clks[] = {
		.base_shift = 0,
		.base_values = crypto_base,
		.n_base_values = ARRAY_SIZE(crypto_base),
	}, {
		.id = EN7581_CLK_EMMC,
		.name = "emmc",

		.base_reg = REG_CRYPTO_CLKSRC2,
		.base_bits = 1,
		.base_shift = 12,
		.base_values = emmc7581_base,
		.n_base_values = ARRAY_SIZE(emmc7581_base),
	}
};

@@ -524,8 +536,6 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat

	hw = en7523_register_pcie_clk(dev, np_base);
	clk_data->hws[EN7523_CLK_PCIE] = hw;

	clk_data->num = EN7523_NUM_CLOCKS;
}

static int en7523_clk_hw_init(struct platform_device *pdev,
@@ -586,8 +596,6 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat

	hw = en7523_register_pcie_clk(dev, base);
	clk_data->hws[EN7523_CLK_PCIE] = hw;

	clk_data->num = EN7523_NUM_CLOCKS;
}

static int en7523_reset_update(struct reset_controller_dev *rcdev,
@@ -701,13 +709,15 @@ static int en7523_clk_probe(struct platform_device *pdev)
	struct clk_hw_onecell_data *clk_data;
	int r;

	soc_data = device_get_match_data(&pdev->dev);

	clk_data = devm_kzalloc(&pdev->dev,
				struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
				struct_size(clk_data, hws, soc_data->num_clocks),
				GFP_KERNEL);
	if (!clk_data)
		return -ENOMEM;

	soc_data = device_get_match_data(&pdev->dev);
	clk_data->num = soc_data->num_clocks;
	r = soc_data->hw_init(pdev, clk_data);
	if (r)
		return r;
@@ -716,6 +726,7 @@ static int en7523_clk_probe(struct platform_device *pdev)
}

static const struct en_clk_soc_data en7523_data = {
	.num_clocks = ARRAY_SIZE(en7523_base_clks) + 1,
	.pcie_ops = {
		.is_enabled = en7523_pci_is_enabled,
		.prepare = en7523_pci_prepare,
@@ -725,6 +736,8 @@ static const struct en_clk_soc_data en7523_data = {
};

static const struct en_clk_soc_data en7581_data = {
	/* We increment num_clocks by 1 to account for additional PCIe clock */
	.num_clocks = ARRAY_SIZE(en7581_base_clks) + 1,
	.pcie_ops = {
		.is_enabled = en7581_pci_is_enabled,
		.enable = en7581_pci_enable,
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