Commit b2fee97e authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-microchip', 'clk-xilinx', 'clk-allwinner', 'clk-imx' and... 

Merge branches 'clk-microchip', 'clk-xilinx', 'clk-allwinner', 'clk-imx' and 'clk-qcom' into clk-next

* clk-microchip:
  clk: at91: sama7d65: add sama7d65 pmc driver
  dt-bindings: clock: Add SAMA7D65 PMC compatible string
  dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65
  clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks
  dt-bindings: clk: at91: Add clock IDs for the slow clock controller

* clk-xilinx:
  clk: clocking-wizard: calculate dividers fractional parts
  dt-bindings: clock: xilinx: Add reset GPIO for VCU
  dt-bindings: clock: xilinx: Convert VCU bindings to dtschema

* clk-allwinner:
  clk: sunxi-ng: h616: Reparent CPU clock during frequency changes
  clk: sunxi-ng: a64: stop force-selecting PLL-MIPI as TCON0 parent
  clk: sunxi-ng: a64: drop redundant CLK_PLL_VIDEO0_2X and CLK_PLL_MIPI
  dt-bindings: clock: sunxi: Export PLL_VIDEO_2X and PLL_MIPI

* clk-imx:
  clk: imx: Apply some clks only for i.MX93
  arm64: dts: imx93: Use IMX93_CLK_SPDIF_IPG as SPDIF IPG clock
  clk: imx93: Add IMX93_CLK_SPDIF_IPG clock
  dt-bindings: clock: imx93: Add SPDIF IPG clk
  clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x
  clk: imx8mp: Fix clkout1/2 support

* clk-qcom: (63 commits)
  clk: qcom: Select CLK_X1E80100_GCC in config CLK_X1P42100_GPUCC
  dt-bindings: clock: move qcom,x1e80100-camcc to its own file
  clk: qcom: smd-rpm: Add clocks for MSM8940
  dt-bindings: clock: qcom,rpmcc: Add MSM8940 compatible
  clk: qcom: smd-rpm: Add clocks for MSM8937
  dt-bindings: clock: qcom,rpmcc: Add MSM8937 compatible
  clk: qcom: ipq5424: Use icc-clk for enabling NoC related clocks
  dt-bindings: interconnect: Add Qualcomm IPQ5424 support
  clk: qcom: Add SM6115 LPASSCC
  dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controller
  clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPs
  clk: qcom: gcc-sdm845: Add general purpose clock ops
  clk: qcom: clk-rcg2: split __clk_rcg2_configure function
  clk: qcom: clk-rcg2: document calc_rate function
  clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSC
  clk: qcom: ipq5424: add gcc_xo_clk
  dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macro
  dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macro
  clk: qcom: ipq5424: remove apss_dbg clock
  dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible
  ...
parents 70741cc3 765ea12f 7681f64e 087b4083 b7efd229 5542b0b5

Documentation/devicetree/bindings/clock/atmel,at91rm9200-pmc.yaml

+2 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ properties: 
              - atmel,sama5d4-pmc

              - microchip,sam9x60-pmc

              - microchip,sam9x7-pmc

              - microchip,sama7d65-pmc

              - microchip,sama7g5-pmc

          - const: syscon
@@ -90,6 +91,7 @@ allOf: 
            enum:

              - microchip,sam9x60-pmc

              - microchip,sam9x7-pmc

              - microchip,sama7d65-pmc

              - microchip,sama7g5-pmc

    then:

      properties:

Documentation/devicetree/bindings/clock/atmel,at91sam9x5-sckc.yaml

+1 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ properties: 
      - items:

          - enum:

              - microchip,sam9x7-sckc

              - microchip,sama7d65-sckc

              - microchip,sama7g5-sckc

          - const: microchip,sam9x60-sckc

Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml

0 → 100644
+77 −0
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm CMN PLL Clock Controller on IPQ SoC



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Luo Jie <quic_luoj@quicinc.com>



description:

  The CMN (or common) PLL clock controller expects a reference

  input clock. This reference clock is from the on-board Wi-Fi.

  The CMN PLL supplies a number of fixed rate output clocks to

  the devices providing networking functions and to GCC. These

  networking hardware include PPE (packet process engine), PCS

  and the externally connected switch or PHY devices. The CMN

  PLL block also outputs fixed rate clocks to GCC. The PLL's

  primary function is to enable fixed rate output clocks for

  networking hardware functions used with the IPQ SoC.



properties:

  compatible:

    enum:

      - qcom,ipq9574-cmn-pll



  reg:

    maxItems: 1



  clocks:

    items:

      - description: The reference clock. The supported clock rates include

          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.

      - description: The AHB clock

      - description: The SYS clock

    description:

      The reference clock is the source clock of CMN PLL, which is from the

      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL

      clock registers.



  clock-names:

    items:

      - const: ref

      - const: ahb

      - const: sys



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>

    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>



    cmn_pll: clock-controller@9b000 {

        compatible = "qcom,ipq9574-cmn-pll";

        reg = <0x0009b000 0x800>;

        clocks = <&cmn_pll_ref_clk>,

                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,

                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;

        clock-names = "ref", "ahb", "sys";

        #clock-cells = <1>;

        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;

        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;

    };

...

Documentation/devicetree/bindings/clock/qcom,mmcc.yaml

+4 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ allOf: 
    then:

      properties:

        clocks:

          minItems: 8

          items:

            - description: Board PXO source

            - description: PLL 3 clock
@@ -87,8 +88,10 @@ allOf: 
            - description: DSI phy instance 2 dsi clock

            - description: DSI phy instance 2 byte clock

            - description: HDMI phy PLL clock

            - description: LVDS PLL clock



        clock-names:

          minItems: 8

          items:

            - const: pxo

            - const: pll3
@@ -98,6 +101,7 @@ allOf: 
            - const: dsi2pll

            - const: dsi2pllbyte

            - const: hdmipll

            - const: lvdspll



  - if:

      properties:

Documentation/devicetree/bindings/clock/qcom,qcs615-gcc.yaml

0 → 100644
+59 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,qcs615-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on QCS615



maintainers:

  - Taniya Das <quic_tdas@quicinc.com>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on QCS615.



  See also: include/dt-bindings/clock/qcom,qcs615-gcc.h



properties:

  compatible:

    const: qcom,qcs615-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Board active XO source

      - description: Sleep clock source



  clock-names:

    items:

      - const: bi_tcxo

      - const: bi_tcxo_ao

      - const: sleep_clk



required:

  - compatible

  - clocks

  - clock-names

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,qcs615-gcc";

      reg = <0x00100000 0x1f0000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>;

      clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...