Commit 217a5f23 authored by David Virag's avatar David Virag Committed by Krzysztof Kozlowski
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clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix 



Update CLKS_NR_FSYS to the proper value after a fix in DT bindings.
This should always be the last clock in a CMU + 1.

Fixes: cd268e30 ("dt-bindings: clock: Add bindings for Exynos7885 CMU_FSYS")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarDavid Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20240806121157.479212-5-virag.david003@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 5828732b

drivers/clk/samsung/clk-exynos7885.c

+1 −1
Original line number Diff line number Diff line
@@ -20,7 +20,7 @@ 
#define CLKS_NR_TOP			(CLK_GOUT_FSYS_USB30DRD + 1)

#define CLKS_NR_CORE			(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)

#define CLKS_NR_PERI			(CLK_GOUT_WDT1_PCLK + 1)

#define CLKS_NR_FSYS			(CLK_GOUT_MMC_SDIO_SDCLKIN + 1)

#define CLKS_NR_FSYS			(CLK_MOUT_FSYS_USB30DRD_USER + 1)



/* ---- CMU_TOP ------------------------------------------------------------- */