Commit 3c5d127f authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull MTD updates from Miquel Raynal:
 "MTD:

   - The Carillo Ranch driver has been removed

   - Top level mtd bindings have received a couple of improvements
     (references, selects)

   - The ssfdc driver received few minor adjustments

   - The usual load of misc/small improvements and fixes

  Raw NAND:

   - The main series brought is an update of the Broadcom support to
     support all BCMBCA SoCs and their specificity (ECC, write
     protection, configuration straps), plus a few misc fixes and
     changes in the main driver. Device tree updates are also part of
     this PR, initially because of a misunderstanding on my side.

   - The STM32_FMC2 controller driver is also upgraded to properly
     support MP1 and MP25 SoCs.

   - A new compatible is added for an Atmel flavor.

   - Among all these feature changes, there is as well a load of
     continuous read related fixes, avoiding more corner conditions and
     clarifying the logic. Finally a few miscellaneous fixes are made to
     the core, the lpx32xx_mlc, fsl_lbc, Meson and Atmel controller
     driver, as well as final one in the Hynix vendor driver.

  SPI-NAND:

   - The ESMT support has been extended to match 5 bytes ID to avoid
     collisions. Winbond support on its side receives support for
     W25N04KV chips.

  SPI NOR:

   - SPI NOR gets the non uniform erase code cleaned. We stopped using
     bitmasks for erase types and flags, and instead introduced
     dedicated members. We then passed the SPI NOR erase map to MTD.
     Users can now determine the erase regions and make informed
     decisions on partitions size.

   - An optional interrupt property is now described in the bindings"

* tag 'mtd/for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (50 commits)
  mtd: rawnand: Ensure continuous reads are well disabled
  mtd: rawnand: Constrain even more when continuous reads are enabled
  mtd: rawnand: brcmnand: Add support for getting ecc setting from strap
  mtd: rawnand: brcmnand: fix sparse warnings
  mtd: nand: raw: atmel: Fix comment in timings preparation
  mtd: rawnand: Ensure all continuous terms are always in sync
  mtd: rawnand: Add a helper for calculating a page index
  mtd: rawnand: Fix and simplify again the continuous read derivations
  mtd: rawnand: hynix: remove @nand_technology kernel-doc description
  dt-bindings: atmel-nand: add microchip,sam9x7-pmecc
  mtd: rawnand: brcmnand: Support write protection setting from dts
  mtd: rawnand: brcmnand: Add BCMBCA read data bus interface
  mtd: rawnand: brcmnand: Rename bcm63138 nand driver
  arm64: dts: broadcom: bcmbca: Update router boards
  arm64: dts: broadcom: bcmbca: Add NAND controller node
  ARM: dts: broadcom: bcmbca: Add NAND controller node
  mtd: spi-nor: core: correct type of i
  mtd: spi-nor: core: set mtd->eraseregions for non-uniform erase map
  mtd: spi-nor: core: get rid of SNOR_OVERLAID_REGION flag
  mtd: spi-nor: core: get rid of SNOR_LAST_REGION flag
  ...
parents 2b3a4192 09888e97
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+1 −0
Original line number Diff line number Diff line
@@ -56,6 +56,7 @@ Required properties:
	"atmel,sama5d4-pmecc"
	"atmel,sama5d2-pmecc"
	"microchip,sam9x60-pmecc"
	"microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"
- reg: should contain 2 register ranges. The first one is pointing to the PMECC
       block, and the second one to the PMECC_ERRLOC block.

+39 −5
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ title: Broadcom STB NAND Controller
maintainers:
  - Brian Norris <computersforpeace@gmail.com>
  - Kamal Dasu <kdasu.kdev@gmail.com>
  - William Zhang <william.zhang@broadcom.com>

description: |
  The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
@@ -18,9 +19,10 @@ description: |
  supports basic PROGRAM and READ functions, among other features.

  This controller was originally designed for STB SoCs (BCM7xxx) but is now
  available on a variety of Broadcom SoCs, including some BCM3xxx, BCM63xx, and
  iProc/Cygnus. Its history includes several similar (but not fully register
  compatible) versions.
  available on a variety of Broadcom SoCs, including some BCM3xxx, MIPS based
  Broadband SoC (BCM63xx), ARM based Broadband SoC (BCMBCA) and iProc/Cygnus.
  Its history includes several similar (but not fully register compatible)
  versions.

  -- Additional SoC-specific NAND controller properties --

@@ -53,7 +55,7 @@ properties:
              - brcm,brcmnand-v7.2
              - brcm,brcmnand-v7.3
          - const: brcm,brcmnand
      - description: BCM63138 SoC-specific NAND controller
      - description: BCMBCA SoC-specific NAND controller
        items:
          - const: brcm,nand-bcm63138
          - enum:
@@ -111,6 +113,13 @@ properties:
      earlier versions of this core that include WP
    type: boolean

  brcm,wp-not-connected:
    description:
      Use this property when WP pin is not physically wired to the NAND chip.
      Write protection feature cannot be used. By default, controller assumes
      the pin is connected and feature is used.
    $ref: /schemas/types.yaml#/definitions/flag

patternProperties:
  "^nand@[a-f0-9]$":
    type: object
@@ -137,6 +146,15 @@ patternProperties:
          layout.
        $ref: /schemas/types.yaml#/definitions/uint32

      brcm,nand-ecc-use-strap:
        description:
          This property requires the host system to get the ECC related
          settings from the SoC NAND boot strap configuration instead of
          the generic NAND ECC settings. This is a common hardware design
          on BCMBCA based boards. This strap ECC option and generic NAND
          ECC option can not be specified at the same time.
        $ref: /schemas/types.yaml#/definitions/flag

    unevaluatedProperties: false

allOf:
@@ -177,6 +195,8 @@ allOf:
            - const: iproc-idm
            - const: iproc-ext
  - if:
      required:
        - interrupts
      properties:
        interrupts:
          minItems: 2
@@ -184,12 +204,26 @@ allOf:
      required:
        - interrupt-names

  - if:
      patternProperties:
        "^nand@[a-f0-9]$":
          required:
            - brcm,nand-ecc-use-strap
    then:
      patternProperties:
        "^nand@[a-f0-9]$":
          properties:
            nand-ecc-strength: false
            nand-ecc-step-size: false
            nand-ecc-maximize: false
            nand-ecc-algo: false
            brcm,nand-oob-sector-size: false

unevaluatedProperties: false

required:
  - reg
  - reg-names
  - interrupts

examples:
  - |
+1 −1
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ Deprecated properties:
				false.

Nand device bindings may contain additional sub-nodes describing partitions of
the address space. See partition.txt for more detail. The NAND Flash timing
the address space. See mtd.yaml for more detail. The NAND Flash timing
values must be programmed in the chip select’s node of AEMIF
memory-controller (see Documentation/devicetree/bindings/memory-controllers/
davinci-aemif.txt).
+1 −1
Original line number Diff line number Diff line
@@ -15,7 +15,7 @@ The DMA fields are not used yet in the driver but are listed here for
completing the bindings.

The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
address space. See mtd.yaml for more detail.

Example:

+1 −1
Original line number Diff line number Diff line
@@ -22,7 +22,7 @@ Deprecated properties:
	(R/B# pins not connected).

Each flash chip described may optionally contain additional sub-nodes
describing partitions of the address space. See partition.txt for more
describing partitions of the address space. See mtd.yaml for more
detail.

Examples:
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