Unverified Commit 3e515fc8 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-socfpga', 'clk-sophgo', 'clk-thead' and 'clk-samsung' into clk-next 

* clk-socfpga:
  clk: socfpga: stratix10: Optimize local variables
  clk: socfpga: clk-pll: Optimize local variables

* clk-sophgo:
  clk: sophgo: Add clock controller support for SG2044 SoC
  clk: sophgo: Add PLL clock controller support for SG2044 SoC
  dt-bindings: clock: sophgo: add clock controller for SG2044
  dt-bindings: soc: sophgo: Add SG2044 top syscon device
  clk: sophgo: Add support for newly added precise compatible
  dt-bindings: clock: sophgo: Use precise compatible for CV1800 series SoC

* clk-thead:
  clk: thead: Add clock support for VO subsystem in T-HEAD TH1520 SoC
  dt-bindings: clock: thead: Add TH1520 VO clock controller

* clk-samsung:
  clk: samsung: correct clock summary for hsi1 block
  clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition
  clk: samsung: exynosautov920: add cpucl1/2 clock support
  dt-bindings: clock: exynosautov920: add cpucl1/2 clock definitions
  clk: samsung: exynosautov920: add cpucl0 clock support
  dt-bindings: clock: exynosautov920: add cpucl0 clock definitions
  clk: samsung: Use samsung CCF common function
parents 7459da16 6bbc69e5 a08f0ac3 29c98b13 3a4c538e

Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml

+69 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: Samsung ExynosAuto v920 SoC clock controller 


maintainers:

  - Sunyeal Hong <sunyeal.hong@samsung.com>

  - Shin Son <shin.son@samsung.com>

  - Chanwoo Choi <cw00.choi@samsung.com>

  - Krzysztof Kozlowski <krzk@kernel.org>

  - Sylwester Nawrocki <s.nawrocki@samsung.com>
@@ -32,6 +33,9 @@ properties: 
  compatible:

    enum:

      - samsung,exynosautov920-cmu-top

      - samsung,exynosautov920-cmu-cpucl0

      - samsung,exynosautov920-cmu-cpucl1

      - samsung,exynosautov920-cmu-cpucl2

      - samsung,exynosautov920-cmu-peric0

      - samsung,exynosautov920-cmu-peric1

      - samsung,exynosautov920-cmu-misc
@@ -69,6 +73,71 @@ allOf: 
          items:

            - const: oscclk



  - if:

      properties:

        compatible:

          contains:

            enum:

              - samsung,exynosautov920-cmu-cpucl0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_CPUCL0 SWITCH clock (from CMU_TOP)

            - description: CMU_CPUCL0 CLUSTER clock (from CMU_TOP)

            - description: CMU_CPUCL0 DBG clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: switch

            - const: cluster

            - const: dbg



  - if:

      properties:

        compatible:

          contains:

            enum:

              - samsung,exynosautov920-cmu-cpucl1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_CPUCL1 SWITCH clock (from CMU_TOP)

            - description: CMU_CPUCL1 CLUSTER clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: switch

            - const: cluster



  - if:

      properties:

        compatible:

          contains:

            enum:

              - samsung,exynosautov920-cmu-cpucl2



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (38.4 MHz)

            - description: CMU_CPUCL2 SWITCH clock (from CMU_TOP)

            - description: CMU_CPUCL2 CLUSTER clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: switch

            - const: cluster



  - if:

      properties:

        compatible:

Documentation/devicetree/bindings/clock/sophgo,cv1800-clk.yaml

+12 −4
Original line number Diff line number Diff line
@@ -11,10 +11,18 @@ maintainers: 


properties:

  compatible:

    enum:

      - sophgo,cv1800-clk

      - sophgo,cv1810-clk

    oneOf:

      - enum:

          - sophgo,cv1800b-clk

          - sophgo,cv1812h-clk

          - sophgo,sg2000-clk

      - items:

          - const: sophgo,sg2002-clk

          - const: sophgo,sg2000-clk

      - const: sophgo,cv1800-clk

        deprecated: true

      - const: sophgo,cv1810-clk

        deprecated: true



  reg:

    maxItems: 1

Documentation/devicetree/bindings/clock/sophgo,sg2044-clk.yaml

0 → 100644
+99 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/sophgo,sg2044-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2044 Clock Controller



maintainers:

  - Inochi Amaoto <inochiama@gmail.com>



description: |

  The Sophgo SG2044 clock controller requires an external oscillator

  as input clock.



  All available clocks are defined as preprocessor macros in

  include/dt-bindings/clock/sophgo,sg2044-clk.h



properties:

  compatible:

    const: sophgo,sg2044-clk



  reg:

    maxItems: 1



  clocks:

    items:

      - description: fpll0

      - description: fpll1

      - description: fpll2

      - description: dpll0

      - description: dpll1

      - description: dpll2

      - description: dpll3

      - description: dpll4

      - description: dpll5

      - description: dpll6

      - description: dpll7

      - description: mpll0

      - description: mpll1

      - description: mpll2

      - description: mpll3

      - description: mpll4

      - description: mpll5



  clock-names:

    items:

      - const: fpll0

      - const: fpll1

      - const: fpll2

      - const: dpll0

      - const: dpll1

      - const: dpll2

      - const: dpll3

      - const: dpll4

      - const: dpll5

      - const: dpll6

      - const: dpll7

      - const: mpll0

      - const: mpll1

      - const: mpll2

      - const: mpll3

      - const: mpll4

      - const: mpll5



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/sophgo,sg2044-pll.h>



    clock-controller@50002000 {

      compatible = "sophgo,sg2044-clk";

      reg = <0x50002000 0x1000>;

      #clock-cells = <1>;

      clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,

               <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,

               <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,

               <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,

               <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,

               <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,

               <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,

               <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,

               <&syscon CLK_MPLL5>;

      clock-names = "fpll0", "fpll1", "fpll2", "dpll0",

                    "dpll1", "dpll2", "dpll3", "dpll4",

                    "dpll5", "dpll6", "dpll7", "mpll0",

                    "mpll1", "mpll2", "mpll3", "mpll4",

                    "mpll5";

    };

Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml

+14 −3
Original line number Diff line number Diff line
@@ -8,7 +8,8 @@ title: T-HEAD TH1520 AP sub-system clock controller 


description: |

  The T-HEAD TH1520 AP sub-system clock controller configures the

  CPU, DPU, GMAC and TEE PLLs.

  CPU, DPU, GMAC and TEE PLLs. Additionally the VO subsystem configures

  the clock gates for the HDMI, MIPI and the GPU.



  SoC reference manual

  https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf
@@ -20,14 +21,24 @@ maintainers: 


properties:

  compatible:

    const: thead,th1520-clk-ap

    enum:

      - thead,th1520-clk-ap

      - thead,th1520-clk-vo



  reg:

    maxItems: 1



  clocks:

    items:

      - description: main oscillator (24MHz)

      - description: |

          One input clock:

          - For "thead,th1520-clk-ap": the clock input must be the 24 MHz

            main oscillator.

          - For "thead,th1520-clk-vo": the clock input must be the VIDEO_PLL,

            which is configured by the AP clock controller. According to the

            TH1520 manual, VIDEO_PLL is a Silicon Creations Sigma-Delta PLL

            (integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with

            a maximum FOUTVCO of 2376 MHz.



  "#clock-cells":

    const: 1

Documentation/devicetree/bindings/soc/sophgo/sophgo,sg2044-top-syscon.yaml

0 → 100644
+49 −0
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/sophgo/sophgo,sg2044-top-syscon.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Sophgo SG2044 SoC TOP system controller



maintainers:

  - Inochi Amaoto <inochiama@gmail.com>



description:

  The Sophgo SG2044 TOP system controller is a hardware block grouping

  multiple small functions, such as clocks and some other internal

  function.



properties:

  compatible:

    items:

      - const: sophgo,sg2044-top-syscon

      - const: syscon



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 1

    description:

      See <dt-bindings/clock/sophgo,sg2044-pll.h> for valid clock.



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    syscon@50000000 {

      compatible = "sophgo,sg2044-top-syscon", "syscon";

      reg = <0x50000000 0x1000>;

      #clock-cells = <1>;

      clocks = <&osc>;

    };