Commit a74bb5f2 authored by Mikhail Paulyshka's avatar Mikhail Paulyshka Committed by Borislav Petkov (AMD)
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x86/CPU/AMD: Disable INVLPGB on Zen2 



AMD Cyan Skillfish (Family 17h, Model 47h, Stepping 0h) has an issue
that causes system oopses and panics when performing TLB flush using
INVLPGB.

However, the problem is that that machine has misconfigured CPUID and
should not report the INVLPGB bit in the first place. So zap the
kernel's representation of the flag so that nothing gets confused.

  [ bp: Massage. ]

Fixes: 767ae437 ("x86/mm: Add INVLPGB feature and Kconfig entry")
Signed-off-by: default avatarMikhail Paulyshka <me@mixaill.net>
Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
Cc: <stable@kernel.org>
Link: https://lore.kernel.org/r/1ebe845b-322b-4929-9093-b41074e9e939@mixaill.net
parent 5b937a1e

arch/x86/kernel/cpu/amd.c

+3 −0
Original line number Diff line number Diff line
@@ -937,6 +937,9 @@ static void init_amd_zen2(struct cpuinfo_x86 *c) 
		msr_clear_bit(MSR_AMD64_CPUID_FN_7, 18);

		pr_emerg("RDSEED is not reliable on this platform; disabling.\n");

	}



	/* Correct misconfigured CPUID on some clients. */

	clear_cpu_cap(c, X86_FEATURE_INVLPGB);

}



static void init_amd_zen3(struct cpuinfo_x86 *c)