Unverified Commit c4ebd661 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'riscv-cache-for-v6.18' of... 

Merge tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into soc/drivers

RISC-V cache drivers for v6.18

sifive:
Reduce the number of fences issued while flushing. Samuel reports that
this is approximately a 15% speed-up.

ax45mp:
Fix the binding so that it permits the cache-sets setting used by the
recently added QiLai SoC.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'riscv-cache-for-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  cache: sifive_ccache: Optimize cache flushes
  dt-bindings: cache: ax45mp: add 2048 as a supported cache-sets value

Link: https://lore.kernel.org/r/20250924-relenting-aqua-a4a93b89809e@spud


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents a53811fb 941327ca

Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml

+5 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ properties: 
    const: 2



  cache-sets:

    const: 1024

    enum: [1024, 2048]



  cache-size:

    enum: [131072, 262144, 524288, 1048576, 2097152]
@@ -81,6 +81,10 @@ allOf: 
          const: 2048

        cache-size:

          const: 2097152

    else:

      properties:

        cache-sets:

          const: 1024



examples:

  - |

drivers/cache/sifive_ccache.c

+4 −4
Original line number Diff line number Diff line
@@ -151,16 +151,16 @@ static void ccache_flush_range(phys_addr_t start, size_t len) 
	if (!len)

		return;



	mb();

	mb(); /* complete earlier memory accesses before the cache flush */

	for (line = ALIGN_DOWN(start, SIFIVE_CCACHE_LINE_SIZE); line < end;

			line += SIFIVE_CCACHE_LINE_SIZE) {

#ifdef CONFIG_32BIT

		writel(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);

		writel_relaxed(line >> 4, ccache_base + SIFIVE_CCACHE_FLUSH32);

#else

		writeq(line, ccache_base + SIFIVE_CCACHE_FLUSH64);

		writeq_relaxed(line, ccache_base + SIFIVE_CCACHE_FLUSH64);

#endif

		mb();

	}

	mb(); /* issue later memory accesses after the cache flush */

}



static const struct riscv_nonstd_cache_ops ccache_mgmt_ops __initconst = {