Commit ee2d2a4e authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-aspeed', 'clk-keystone', 'clk-mobileye' and 'clk-allwinner' into clk-next 

* clk-aspeed:
  clk: ast2600: Add FSI parent clock with correct rate
  dt-bindings: clock: ast2600: Add FSI clock

* clk-keystone:
  clk: keystone: sci-clk: Adding support for non contiguous clocks

* clk-mobileye:
  dt-bindings: reset: mobileye,eyeq5-reset: add bindings
  dt-bindings: clock: mobileye,eyeq5-clk: add bindings
  clk: fixed-factor: add fwname-based constructor functions
  clk: fixed-factor: add optional accuracy support

* clk-allwinner:
  clk: sunxi: usb: fix kernel-doc warnings
  clk: sunxi: sun9i-cpus: fix kernel-doc warnings
  clk: sunxi: a20-gmac: fix kernel-doc warnings
parents cf5f06c8 56ce4e73 ad3ac13c c6e0897e 84448fa6

Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml

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+51 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mobileye EyeQ5 clock controller



description:

  The EyeQ5 clock controller handles 10 read-only PLLs derived from the main

  crystal clock. It also exposes one divider clock, a child of one of the PLLs.

  Its registers live in a shared region called OLB.



maintainers:

  - Grégory Clement <gregory.clement@bootlin.com>

  - Théo Lebrun <theo.lebrun@bootlin.com>

  - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>



properties:

  compatible:

    const: mobileye,eyeq5-clk



  reg:

    maxItems: 2



  reg-names:

    items:

      - const: plls

      - const: ospi



  "#clock-cells":

    const: 1



  clocks:

    maxItems: 1

    description:

      Input parent clock to all PLLs. Expected to be the main crystal.



  clock-names:

    items:

      - const: ref



required:

  - compatible

  - reg

  - reg-names

  - "#clock-cells"

  - clocks

  - clock-names



additionalProperties: false

Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml

0 → 100644
+43 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Mobileye EyeQ5 reset controller



description:

  The EyeQ5 reset driver handles three reset domains. Its registers live in a

  shared region called OLB.



maintainers:

  - Grégory Clement <gregory.clement@bootlin.com>

  - Théo Lebrun <theo.lebrun@bootlin.com>

  - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>



properties:

  compatible:

    const: mobileye,eyeq5-reset



  reg:

    maxItems: 3



  reg-names:

    items:

      - const: d0

      - const: d1

      - const: d2



  "#reset-cells":

    const: 2

    description:

      The first cell is the domain (0 to 2 inclusive) and the second one is the

      reset index inside that domain.



required:

  - compatible

  - reg

  - reg-names

  - "#reset-cells"



additionalProperties: false

drivers/clk/clk-ast2600.c

+5 −2
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ 
 * This includes the gates (configured from aspeed_g6_gates), plus the

 * explicitly-configured clocks (ASPEED_CLK_HPLL and up).

 */

#define ASPEED_G6_NUM_CLKS		72

#define ASPEED_G6_NUM_CLKS		73



#define ASPEED_G6_SILICON_REV		0x014

#define CHIP_REVISION_ID			GENMASK(23, 16)
@@ -157,7 +157,7 @@ static const struct aspeed_gate_data aspeed_g6_gates[] = { 
	[ASPEED_CLK_GATE_UART11CLK]	= { 59,  -1, "uart11clk-gate",	"uartx", 0 },	/* UART11 */

	[ASPEED_CLK_GATE_UART12CLK]	= { 60,  -1, "uart12clk-gate",	"uartx", 0 },	/* UART12 */

	[ASPEED_CLK_GATE_UART13CLK]	= { 61,  -1, "uart13clk-gate",	"uartx", 0 },	/* UART13 */

	[ASPEED_CLK_GATE_FSICLK]	= { 62,  59, "fsiclk-gate",	NULL,	 0 },	/* FSI */

	[ASPEED_CLK_GATE_FSICLK]	= { 62,  59, "fsiclk-gate",	"fsiclk", 0 },	/* FSI */

};



static const struct clk_div_table ast2600_eclk_div_table[] = {
@@ -821,6 +821,9 @@ static void __init aspeed_g6_cc(struct regmap *map) 


	hw = clk_hw_register_fixed_factor(NULL, "i3cclk", "apll", 0, 1, 8);

	aspeed_g6_clk_data->hws[ASPEED_CLK_I3C] = hw;



	hw = clk_hw_register_fixed_factor(NULL, "fsiclk", "apll", 0, 1, 4);

	aspeed_g6_clk_data->hws[ASPEED_CLK_FSI] = hw;

};



static void __init aspeed_g6_cc_init(struct device_node *np)

drivers/clk/clk-fixed-factor.c

+87 −16
Original line number Diff line number Diff line
@@ -57,10 +57,22 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, 
	return 0;

}



static unsigned long clk_factor_recalc_accuracy(struct clk_hw *hw,

						unsigned long parent_accuracy)

{

	struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);



	if (fix->flags & CLK_FIXED_FACTOR_FIXED_ACCURACY)

		return fix->acc;



	return parent_accuracy;

}



const struct clk_ops clk_fixed_factor_ops = {

	.round_rate = clk_factor_round_rate,

	.set_rate = clk_factor_set_rate,

	.recalc_rate = clk_factor_recalc_rate,

	.recalc_accuracy = clk_factor_recalc_accuracy,

};

EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
@@ -79,13 +91,12 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void * 
static struct clk_hw *

__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,

		const char *name, const char *parent_name,

		const struct clk_hw *parent_hw, int index,

		const struct clk_hw *parent_hw, const struct clk_parent_data *pdata,

		unsigned long flags, unsigned int mult, unsigned int div,

		bool devm)

		unsigned long acc, unsigned int fixflags, bool devm)

{

	struct clk_fixed_factor *fix;

	struct clk_init_data init = { };

	struct clk_parent_data pdata = { .index = index };

	struct clk_hw *hw;

	int ret;
@@ -105,6 +116,8 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, 
	fix->mult = mult;

	fix->div = div;

	fix->hw.init = &init;

	fix->acc = acc;

	fix->flags = fixflags;



	init.name = name;

	init.ops = &clk_fixed_factor_ops;
@@ -114,7 +127,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, 
	else if (parent_hw)

		init.parent_hws = &parent_hw;

	else

		init.parent_data = &pdata;

		init.parent_data = pdata;

	init.num_parents = 1;



	hw = &fix->hw;
@@ -151,8 +164,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, 
		const char *name, unsigned int index, unsigned long flags,

		unsigned int mult, unsigned int div)

{

	return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index,

					      flags, mult, div, true);

	const struct clk_parent_data pdata = { .index = index };



	return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata,

					      flags, mult, div, 0, 0, true);

}

EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index);
@@ -173,8 +188,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, 
		const char *name, const struct clk_hw *parent_hw,

		unsigned long flags, unsigned int mult, unsigned int div)

{

	const struct clk_parent_data pdata = { .index = -1 };



	return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,

					      -1, flags, mult, div, true);

					      &pdata, flags, mult, div, 0, 0, true);

}

EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw);
@@ -182,9 +199,10 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, 
		const char *name, const struct clk_hw *parent_hw,

		unsigned long flags, unsigned int mult, unsigned int div)

{

	return __clk_hw_register_fixed_factor(dev, NULL, name, NULL,

					      parent_hw, -1, flags, mult, div,

					      false);

	const struct clk_parent_data pdata = { .index = -1 };



	return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,

					      &pdata, flags, mult, div, 0, 0, false);

}

EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw);
@@ -192,11 +210,37 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, 
		const char *name, const char *parent_name, unsigned long flags,

		unsigned int mult, unsigned int div)

{

	return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1,

					      flags, mult, div, false);

	const struct clk_parent_data pdata = { .index = -1 };



	return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,

					      &pdata, flags, mult, div, 0, 0, false);

}

EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);



struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,

		struct device_node *np, const char *name, const char *fw_name,

		unsigned long flags, unsigned int mult, unsigned int div)

{

	const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name };



	return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL,

			&pdata, flags, mult, div, 0, 0, false);

}

EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_fwname);



struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,

		struct device_node *np, const char *name, const char *fw_name,

		unsigned long flags, unsigned int mult, unsigned int div,

		unsigned long acc)

{

	const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name };



	return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL,

			&pdata, flags, mult, div, acc,

			CLK_FIXED_FACTOR_FIXED_ACCURACY, false);

}

EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy_fwname);



struct clk *clk_register_fixed_factor(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,

		unsigned int mult, unsigned int div)
@@ -239,16 +283,43 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, 
		const char *name, const char *parent_name, unsigned long flags,

		unsigned int mult, unsigned int div)

{

	return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1,

			flags, mult, div, true);

	const struct clk_parent_data pdata = { .index = -1 };



	return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,

			&pdata, flags, mult, div, 0, 0, true);

}

EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);



struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,

		struct device_node *np, const char *name, const char *fw_name,

		unsigned long flags, unsigned int mult, unsigned int div)

{

	const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name };



	return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL,

			&pdata, flags, mult, div, 0, 0, true);

}

EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_fwname);



struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,

		struct device_node *np, const char *name, const char *fw_name,

		unsigned long flags, unsigned int mult, unsigned int div,

		unsigned long acc)

{

	const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name };



	return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL,

			&pdata, flags, mult, div, acc,

			CLK_FIXED_FACTOR_FIXED_ACCURACY, true);

}

EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_with_accuracy_fwname);



#ifdef CONFIG_OF

static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)

{

	struct clk_hw *hw;

	const char *clk_name = node->name;

	const struct clk_parent_data pdata = { .index = 0 };

	u32 div, mult;

	int ret;
@@ -266,8 +337,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) 


	of_property_read_string(node, "clock-output-names", &clk_name);



	hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0,

					    0, mult, div, false);

	hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL,

					    &pdata, 0, mult, div, 0, 0, false);

	if (IS_ERR(hw)) {

		/*

		 * Clear OF_POPULATED flag so that clock registration can be

drivers/clk/keystone/sci-clk.c

+10 −0
Original line number Diff line number Diff line
@@ -516,6 +516,7 @@ static int ti_sci_scan_clocks_from_dt(struct sci_clk_provider *provider) 
	struct sci_clk *sci_clk, *prev;

	int num_clks = 0;

	int num_parents;

	bool state;

	int clk_id;

	const char * const clk_names[] = {

		"clocks", "assigned-clocks", "assigned-clock-parents", NULL
@@ -586,6 +587,15 @@ static int ti_sci_scan_clocks_from_dt(struct sci_clk_provider *provider) 
				clk_id = args.args[1] + 1;



				while (num_parents--) {

					/* Check if this clock id is valid */

					ret = provider->ops->is_auto(provider->sci,

						sci_clk->dev_id, clk_id, &state);



					if (ret) {

						clk_id++;

						continue;

					}



					sci_clk = devm_kzalloc(dev,

							       sizeof(*sci_clk),

							       GFP_KERNEL);