Commit f6d9883f authored by Namhyung Kim's avatar Namhyung Kim
Browse files

tools/include: Sync x86 headers with the kernel sources 



To pick up changes from:

  149fd471 perf/x86/intel: Support Perfmon MSRs aliasing
  21b362cc x86/resctrl: Enable shared RMID mode on Sub-NUMA Cluster (SNC) systems
  4f460bff cpufreq: acpi: move MSR_K7_HWCR_CPB_DIS_BIT into msr-index.h
  7ea81936 x86/cpufeatures: Add HWP highest perf change feature flag
  78ce84b9 x86/cpufeatures: Flip the /proc/cpuinfo appearance logic
  1beb348d x86/sev: Provide SVSM discovery support

This should be used to beautify x86 syscall arguments and it addresses
these tools/perf build warnings:

  Warning: Kernel ABI header differences:
  diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h
  diff -u tools/arch/x86/include/asm/msr-index.h arch/x86/include/asm/msr-index.h

Please see tools/include/uapi/README for details (it's in the first patch
of this series).

Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Signed-off-by: default avatarNamhyung Kim <namhyung@kernel.org>
parent 845295f4

tools/arch/x86/include/asm/cpufeatures.h

+403 −400

File changed.

Preview size limit exceeded, changes collapsed.

tools/arch/x86/include/asm/msr-index.h

+11 −0
Original line number Diff line number Diff line
@@ -566,6 +566,12 @@ 
#define MSR_RELOAD_PMC0			0x000014c1

#define MSR_RELOAD_FIXED_CTR0		0x00001309



/* V6 PMON MSR range */

#define MSR_IA32_PMC_V6_GP0_CTR		0x1900

#define MSR_IA32_PMC_V6_GP0_CFG_A	0x1901

#define MSR_IA32_PMC_V6_FX0_CTR		0x1980

#define MSR_IA32_PMC_V6_STEP		4



/* KeyID partitioning between MKTME and TDX */

#define MSR_IA32_MKTME_KEYID_PARTITIONING	0x00000087
@@ -660,6 +666,8 @@ 
#define MSR_AMD64_RMP_BASE		0xc0010132

#define MSR_AMD64_RMP_END		0xc0010133



#define MSR_SVSM_CAA			0xc001f000



/* AMD Collaborative Processor Performance Control MSRs */

#define MSR_AMD_CPPC_CAP1		0xc00102b0

#define MSR_AMD_CPPC_ENABLE		0xc00102b1
@@ -781,6 +789,8 @@ 
#define MSR_K7_HWCR_IRPERF_EN		BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)

#define MSR_K7_FID_VID_CTL		0xc0010041

#define MSR_K7_FID_VID_STATUS		0xc0010042

#define MSR_K7_HWCR_CPB_DIS_BIT		25

#define MSR_K7_HWCR_CPB_DIS		BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT)



/* K6 MSRs */

#define MSR_K6_WHCR			0xc0000082
@@ -1164,6 +1174,7 @@ 
#define MSR_IA32_QM_CTR			0xc8e

#define MSR_IA32_PQR_ASSOC		0xc8f

#define MSR_IA32_L3_CBM_BASE		0xc90

#define MSR_RMID_SNC_CONFIG		0xca0

#define MSR_IA32_L2_CBM_BASE		0xd10

#define MSR_IA32_MBA_THRTL_BASE		0xd50