Unverified Commit f700b882 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.19-tag2' of... 

Merge tag 'renesas-clk-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add GPU clocks on R-Car V3U
 - Add USB3.0 clocks and resets on RZ/V2H and RZ/V2N
 - Add more serial (RSCI) clocks and resets on RZ/G3E
 - Add SPI clocks on RZ/T2H and RZ/N2H

* tag 'renesas-clk-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a09g077: Add SPI module clocks
  clk: renesas: r9a09g056: Add USB3.0 clocks/resets
  clk: renesas: r9a09g057: Add USB3.0 clocks/resets
  clk: renesas: r9a09g047: Add RSCI clocks/resets
  dt-bindings: clock: renesas,r9a09g056-cpg: Add USB3.0 core clocks
  dt-bindings: clock: renesas,r9a09g057-cpg: Add USB3.0 core clocks
  clk: renesas: r9a06g032: Fix memory leak in error path
  clk: renesas: r9a09g077: Use devm_ helpers for divider clock registration
  clk: renesas: r9a09g077: Remove stray blank line
  clk: renesas: r9a09g077: Propagate rate changes to parent clocks
  clk: renesas: r8a779a0: Add 3DGE module clock
  clk: renesas: r8a779a0: Add ZG Core clock
  clk: renesas: rcar-gen4: Add support for clock dividers in FRQCRB
  dt-bindings: clock: r8a779a0: Add ZG core clock
parents 1f2d68c3 5fb2f673

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+6 −1
Original line number Diff line number Diff line
@@ -26,7 +26,7 @@ 


enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R8A779A0_CLK_OSC,

	LAST_DT_CORE_CLK = R8A779A0_CLK_ZG,



	/* External Input Clocks */

	CLK_EXTAL,
@@ -39,6 +39,7 @@ enum clk_ids { 
	CLK_PLL21,

	CLK_PLL30,

	CLK_PLL31,

	CLK_PLL4,

	CLK_PLL5,

	CLK_PLL1_DIV2,

	CLK_PLL20_DIV2,
@@ -65,6 +66,7 @@ enum clk_ids { 
#define CPG_PLL21CR	0x0838	/* PLL21 Control Register */

#define CPG_PLL30CR	0x083c	/* PLL30 Control Register */

#define CPG_PLL31CR	0x0840	/* PLL31 Control Register */

#define CPG_PLL4CR	0x0844	/* PLL4 Control Register */



static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {

	/* External Clock Inputs */
@@ -79,6 +81,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	DEF_PLL(".pll21", CLK_PLL21,	CPG_PLL21CR),

	DEF_PLL(".pll30", CLK_PLL30,	CPG_PLL30CR),

	DEF_PLL(".pll31", CLK_PLL31,	CPG_PLL31CR),

	DEF_PLL(".pll4",  CLK_PLL4,	CPG_PLL4CR),



	DEF_FIXED(".pll1_div2",		CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),

	DEF_FIXED(".pll20_div2",	CLK_PLL20_DIV2,	CLK_PLL20,	2, 1),
@@ -98,6 +101,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
	/* Core Clock Outputs */

	DEF_GEN4_Z("z0",	R8A779A0_CLK_Z0,	CLK_TYPE_GEN4_Z,	CLK_PLL20,	2, 0),

	DEF_GEN4_Z("z1",	R8A779A0_CLK_Z1,	CLK_TYPE_GEN4_Z,	CLK_PLL21,	2, 8),

	DEF_GEN4_Z("zg",	R8A779A0_CLK_ZG,	CLK_TYPE_GEN4_Z,	CLK_PLL4,	2, 88),

	DEF_FIXED("zx",		R8A779A0_CLK_ZX,	CLK_PLL20_DIV2,	2, 1),

	DEF_FIXED("s1d1",	R8A779A0_CLK_S1D1,	CLK_S1,		1, 1),

	DEF_FIXED("s1d2",	R8A779A0_CLK_S1D2,	CLK_S1,		2, 1),
@@ -138,6 +142,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {

	DEF_MOD("3dge",		  0,	R8A779A0_CLK_ZG),

	DEF_MOD("isp0",		 16,	R8A779A0_CLK_S1D1),

	DEF_MOD("isp1",		 17,	R8A779A0_CLK_S1D1),

	DEF_MOD("isp2",		 18,	R8A779A0_CLK_S1D1),

drivers/clk/renesas/r9a06g032-clocks.c

+3 −3
Original line number Diff line number Diff line
@@ -1333,9 +1333,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) 
	if (IS_ERR(mclk))

		return PTR_ERR(mclk);



	clocks->reg = of_iomap(np, 0);

	if (WARN_ON(!clocks->reg))

		return -ENOMEM;

	clocks->reg = devm_of_iomap(dev, np, 0, NULL);

	if (IS_ERR(clocks->reg))

		return PTR_ERR(clocks->reg);



	r9a06g032_init_h2mode(clocks);

drivers/clk/renesas/r9a09g047-cpg.c

+126 −0
Original line number Diff line number Diff line
@@ -44,6 +44,9 @@ enum clk_ids { 
	CLK_PLLCLN_DIV8,

	CLK_PLLCLN_DIV16,

	CLK_PLLCLN_DIV20,

	CLK_PLLCLN_DIV64,

	CLK_PLLCLN_DIV256,

	CLK_PLLCLN_DIV1024,

	CLK_PLLDTY_ACPU,

	CLK_PLLDTY_ACPU_DIV2,

	CLK_PLLDTY_ACPU_DIV4,
@@ -142,6 +145,9 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { 
	DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8),

	DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16),

	DEF_FIXED(".pllcln_div20", CLK_PLLCLN_DIV20, CLK_PLLCLN, 1, 20),

	DEF_FIXED(".pllcln_div64", CLK_PLLCLN_DIV64, CLK_PLLCLN, 1, 64),

	DEF_FIXED(".pllcln_div256", CLK_PLLCLN_DIV256, CLK_PLLCLN, 1, 256),

	DEF_FIXED(".pllcln_div1024", CLK_PLLCLN_DIV1024, CLK_PLLCLN, 1, 1024),



	DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),

	DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2),
@@ -218,6 +224,106 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = { 
						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("wdt_3_clk_loco",		CLK_QEXTAL, 5, 2, 2, 18,

						BUS_MSTOP(5, BIT(13))),

	DEF_MOD("rsci0_pclk",			CLK_PLLCLN_DIV16, 5, 13, 2, 29,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_tclk",			CLK_PLLCLN_DIV16, 5, 14, 2, 30,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_ps_ps3_n",		CLK_PLLCLN_DIV1024, 5, 15, 2, 31,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 0, 3, 0,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci0_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 1, 3, 1,

						BUS_MSTOP(11, BIT(3))),

	DEF_MOD("rsci1_pclk",			CLK_PLLCLN_DIV16, 6, 2, 3, 2,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_tclk",			CLK_PLLCLN_DIV16, 6, 3, 3, 3,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 4, 3, 4,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 5, 3, 5,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci1_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 6, 3, 6,

						BUS_MSTOP(11, BIT(4))),

	DEF_MOD("rsci2_pclk",			CLK_PLLCLN_DIV16, 6, 7, 3, 7,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_tclk",			CLK_PLLCLN_DIV16, 6, 8, 3, 8,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 9, 3, 9,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 10, 3, 10,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci2_ps_ps1_n",		CLK_PLLCLN_DIV64, 6, 11, 3, 11,

						BUS_MSTOP(11, BIT(5))),

	DEF_MOD("rsci3_pclk",			CLK_PLLCLN_DIV16, 6, 12, 3, 12,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_tclk",			CLK_PLLCLN_DIV16, 6, 13, 3, 13,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_ps_ps3_n",		CLK_PLLCLN_DIV1024, 6, 14, 3, 14,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_ps_ps2_n",		CLK_PLLCLN_DIV256, 6, 15, 3, 15,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci3_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 0, 3, 16,

						BUS_MSTOP(11, BIT(6))),

	DEF_MOD("rsci4_pclk",			CLK_PLLCLN_DIV16, 7, 1, 3, 17,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_tclk",			CLK_PLLCLN_DIV16, 7, 2, 3, 18,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 3, 3, 19,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 4, 3, 20,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci4_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 5, 3, 21,

						BUS_MSTOP(11, BIT(7))),

	DEF_MOD("rsci5_pclk",			CLK_PLLCLN_DIV16, 7, 6, 3, 22,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_tclk",			CLK_PLLCLN_DIV16, 7, 7, 3, 23,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 8, 3, 24,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 9, 3, 25,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci5_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 10, 3, 26,

						BUS_MSTOP(11, BIT(8))),

	DEF_MOD("rsci6_pclk",			CLK_PLLCLN_DIV16, 7, 11, 3, 27,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_tclk",			CLK_PLLCLN_DIV16, 7, 12, 3, 28,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_ps_ps3_n",		CLK_PLLCLN_DIV1024, 7, 13, 3, 29,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_ps_ps2_n",		CLK_PLLCLN_DIV256, 7, 14, 3, 30,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci6_ps_ps1_n",		CLK_PLLCLN_DIV64, 7, 15, 3, 31,

						BUS_MSTOP(11, BIT(9))),

	DEF_MOD("rsci7_pclk",			CLK_PLLCLN_DIV16, 8, 0, 4, 0,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_tclk",			CLK_PLLCLN_DIV16, 8, 1, 4, 1,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 2, 4, 2,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 3, 4, 3,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci7_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 4, 4, 4,

						BUS_MSTOP(11, BIT(10))),

	DEF_MOD("rsci8_pclk",			CLK_PLLCLN_DIV16, 8, 5, 4, 5,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_tclk",			CLK_PLLCLN_DIV16, 8, 6, 4, 6,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 7, 4, 7,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 8, 4, 8,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci8_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 9, 4, 9,

						BUS_MSTOP(11, BIT(11))),

	DEF_MOD("rsci9_pclk",			CLK_PLLCLN_DIV16, 8, 10, 4, 10,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_tclk",			CLK_PLLCLN_DIV16, 8, 11, 4, 11,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps3_n",		CLK_PLLCLN_DIV1024, 8, 12, 4, 12,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps2_n",		CLK_PLLCLN_DIV256, 8, 13, 4, 13,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("rsci9_ps_ps1_n",		CLK_PLLCLN_DIV64, 8, 14, 4, 14,

						BUS_MSTOP(11, BIT(12))),

	DEF_MOD("scif_0_clk_pck",		CLK_PLLCM33_DIV16, 8, 15, 4, 15,

						BUS_MSTOP(3, BIT(14))),

	DEF_MOD("i3c_0_pclkrw",			CLK_PLLCLN_DIV16, 9, 0, 4, 16,
@@ -351,6 +457,26 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = { 
	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */

	DEF_RST(7, 7, 3, 8),		/* WDT_2_RESET */

	DEF_RST(7, 8, 3, 9),		/* WDT_3_RESET */

	DEF_RST(8, 1, 3, 18),		/* RSCI0_PRESETN */

	DEF_RST(8, 2, 3, 19),		/* RSCI0_TRESETN */

	DEF_RST(8, 3, 3, 20),		/* RSCI1_PRESETN */

	DEF_RST(8, 4, 3, 21),		/* RSCI1_TRESETN */

	DEF_RST(8, 5, 3, 22),		/* RSCI2_PRESETN */

	DEF_RST(8, 6, 3, 23),		/* RSCI2_TRESETN */

	DEF_RST(8, 7, 3, 24),		/* RSCI3_PRESETN */

	DEF_RST(8, 8, 3, 25),		/* RSCI3_TRESETN */

	DEF_RST(8, 9, 3, 26),		/* RSCI4_PRESETN */

	DEF_RST(8, 10, 3, 27),		/* RSCI4_TRESETN */

	DEF_RST(8, 11, 3, 28),		/* RSCI5_PRESETN */

	DEF_RST(8, 12, 3, 29),		/* RSCI5_TRESETN */

	DEF_RST(8, 13, 3, 30),		/* RSCI6_PRESETN */

	DEF_RST(8, 14, 3, 31),		/* RSCI6_TRESETN */

	DEF_RST(8, 15, 4, 0),		/* RSCI7_PRESETN */

	DEF_RST(9, 0, 4, 1),		/* RSCI7_TRESETN */

	DEF_RST(9, 1, 4, 2),		/* RSCI8_PRESETN */

	DEF_RST(9, 2, 4, 3),		/* RSCI8_TRESETN */

	DEF_RST(9, 3, 4, 4),		/* RSCI9_PRESETN */

	DEF_RST(9, 4, 4, 5),		/* RSCI9_TRESETN */

	DEF_RST(9, 5, 4, 6),		/* SCIF_0_RST_SYSTEM_N */

	DEF_RST(9, 6, 4, 7),		/* I3C_0_PRESETN */

	DEF_RST(9, 7, 4, 8),		/* I3C_0_TRESETN */

drivers/clk/renesas/r9a09g056-cpg.c

+8 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 


enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A09G056_SPI_CLK_SPI,

	LAST_DT_CORE_CLK = R9A09G056_USB3_0_CLKCORE,



	/* External Input Clocks */

	CLK_AUDIO_EXTAL,
@@ -226,6 +226,8 @@ static const struct cpg_core_clk r9a09g056_core_clks[] __initconst = { 
		  CLK_PLLETH_DIV_125_FIX, 1, 1),

	DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G056_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,

			     FIXED_MOD_CONF_XSPI),

	DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G056_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),

	DEF_FIXED("usb3_0_core_clk", R9A09G056_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),

};



static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = {
@@ -319,6 +321,10 @@ static const struct rzv2h_mod_clk r9a09g056_mod_clks[] __initconst = { 
						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,

						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("usb3_0_aclk",			CLK_PLLDTY_DIV8, 10, 15, 5, 15,

						BUS_MSTOP(7, BIT(12))),

	DEF_MOD("usb3_0_pclk_usbtst",		CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,

						BUS_MSTOP(7, BIT(14))),

	DEF_MOD("usb2_0_u2h0_hclk",		CLK_PLLDTY_DIV8, 11, 3, 5, 19,

						BUS_MSTOP(7, BIT(7))),

	DEF_MOD("usb2_0_u2p_exr_cpuclk",	CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21,
@@ -426,6 +432,7 @@ static const struct rzv2h_reset r9a09g056_resets[] __initconst = { 
	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */

	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */

	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */

	DEF_RST(10, 10, 4, 27),		/* USB3_0_ARESETN */

	DEF_RST(10, 12, 4, 29),		/* USB2_0_U2H0_HRESETN */

	DEF_RST(10, 14, 4, 31),		/* USB2_0_U2P_EXL_SYSRST */

	DEF_RST(10, 15, 5, 0),		/* USB2_0_PRESETN */

drivers/clk/renesas/r9a09g057-cpg.c

+15 −1
Original line number Diff line number Diff line
@@ -17,7 +17,7 @@ 


enum clk_ids {

	/* Core Clock Outputs exported to DT */

	LAST_DT_CORE_CLK = R9A09G057_SPI_CLK_SPI,

	LAST_DT_CORE_CLK = R9A09G057_USB3_1_CLKCORE,



	/* External Input Clocks */

	CLK_AUDIO_EXTAL,
@@ -235,6 +235,10 @@ static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 
		  CLK_PLLETH_DIV_125_FIX, 1, 1),

	DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2,

			     FIXED_MOD_CONF_XSPI),

	DEF_FIXED("usb3_0_ref_alt_clk_p", R9A09G057_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),

	DEF_FIXED("usb3_0_core_clk", R9A09G057_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),

	DEF_FIXED("usb3_1_ref_alt_clk_p", R9A09G057_USB3_1_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),

	DEF_FIXED("usb3_1_core_clk", R9A09G057_USB3_1_CLKCORE, CLK_QEXTAL, 1, 1),

};



static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = {
@@ -360,6 +364,14 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 
						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,

						BUS_MSTOP(8, BIT(4))),

	DEF_MOD("usb3_0_aclk",			CLK_PLLDTY_DIV8, 10, 15, 5, 15,

						BUS_MSTOP(7, BIT(12))),

	DEF_MOD("usb3_0_pclk_usbtst",		CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,

						BUS_MSTOP(7, BIT(14))),

	DEF_MOD("usb3_1_aclk",			CLK_PLLDTY_DIV8, 11, 1, 5, 17,

						BUS_MSTOP(7, BIT(13))),

	DEF_MOD("usb3_1_pclk_usbtst",		CLK_PLLDTY_ACPU_DIV4, 11, 2, 5, 18,

						BUS_MSTOP(7, BIT(15))),

	DEF_MOD("usb2_0_u2h0_hclk",		CLK_PLLDTY_DIV8, 11, 3, 5, 19,

						BUS_MSTOP(7, BIT(7))),

	DEF_MOD("usb2_0_u2h1_hclk",		CLK_PLLDTY_DIV8, 11, 4, 5, 20,
@@ -501,6 +513,8 @@ static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 
	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */

	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */

	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */

	DEF_RST(10, 10, 4, 27),		/* USB3_0_ARESETN */

	DEF_RST(10, 11, 4, 28),		/* USB3_1_ARESETN */

	DEF_RST(10, 12, 4, 29),		/* USB2_0_U2H0_HRESETN */

	DEF_RST(10, 13, 4, 30),		/* USB2_0_U2H1_HRESETN */

	DEF_RST(10, 14, 4, 31),		/* USB2_0_U2P_EXL_SYSRST */