Commit 21a5352d authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-marvell', 'clk-adi', 'clk-qcom' and 'clk-devm' into clk-next 

 - Add devm_clk_bulk_get_all_enabled() to return number of clks acquired
 - Marvell PXA1908 SoC clks

* clk-marvell:
  clk: mmp: Add Marvell PXA1908 MPMU driver
  clk: mmp: Add Marvell PXA1908 APMU driver
  clk: mmp: Add Marvell PXA1908 APBCP driver
  clk: mmp: Add Marvell PXA1908 APBC driver
  dt-bindings: clock: Add Marvell PXA1908 clock bindings
  clk: mmp: Switch to use struct u32_fract instead of custom one

* clk-adi:
  clk: clk-axi-clkgen: make sure to enable the AXI bus clock
  dt-bindings: clock: axi-clkgen: include AXI clk

* clk-qcom: (43 commits)
  clk: qcom: remove unused data from gcc-ipq5424.c
  clk: qcom: Add support for Global Clock Controller on QCS8300
  dt-bindings: clock: qcom: Add GCC clocks for QCS8300
  clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC
  clk: qcom: clk-alpha-pll: Add NSS HUAYRA ALPHA PLL support for ipq9574
  dt-bindings: clock: Add Qualcomm IPQ5424 GCC binding
  clk: qcom: add SAR2130P GPU Clock Controller support
  clk: qcom: dispcc-sm8550: enable support for SAR2130P
  clk: qcom: tcsrcc-sm8550: add SAR2130P support
  clk: qcom: add support for GCC on SAR2130P
  clk: qcom: rpmh: add support for SAR2130P
  clk: qcom: rcg2: add clk_rcg2_shared_floor_ops
  dt-bindings: clk: qcom,sm8450-gpucc: add SAR2130P compatibles
  dt-bindings: clock: qcom,sm8550-dispcc: Add SAR2130P compatible
  dt-bindings: clock: qcom,sm8550-tcsr: Add SAR2130P compatible
  dt-bindings: clock: qcom: document SAR2130P Global Clock Controller
  dt-bindings: clock: qcom,rpmhcc: Add SAR2130P compatible
  clk: qcom: Make GCC_6125 depend on QCOM_GDSC
  dt-bindings: clock: qcom: gcc-ipq9574: remove q6 bring up clock macros
  dt-bindings: clock: qcom: gcc-ipq5332: remove q6 bring up clock macros
  ...

* clk-devm:
  clk: Provide devm_clk_bulk_get_all_enabled() helper
parents 0cf32b1f ebac87cd c64ef7e4 4adb9201 51e32e89

Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml

+18 −4
Original line number Diff line number Diff line
@@ -26,9 +26,21 @@ properties: 
    description:

      Specifies the reference clock(s) from which the output frequency is

      derived. This must either reference one clock if only the first clock

      input is connected or two if both clock inputs are connected.

    minItems: 1

    maxItems: 2

      input is connected or two if both clock inputs are connected. The last

      clock is the AXI bus clock that needs to be enabled so we can access the

      core registers.

    minItems: 2

    maxItems: 3



  clock-names:

    oneOf:

      - items:

          - const: clkin1

          - const: s_axi_aclk

      - items:

          - const: clkin1

          - const: clkin2

          - const: s_axi_aclk



  '#clock-cells':

    const: 0
@@ -40,6 +52,7 @@ required: 
  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false
@@ -50,5 +63,6 @@ examples: 
      compatible = "adi,axi-clkgen-2.00.a";

      #clock-cells = <0>;

      reg = <0xff000000 0x1000>;

      clocks = <&osc 1>;

      clocks = <&osc 1>, <&clkc 15>;

      clock-names = "clkin1", "s_axi_aclk";

    };

Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml

0 → 100644
+48 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/marvell,pxa1908.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Marvell PXA1908 Clock Controllers



maintainers:

  - Duje Mihanović <duje.mihanovic@skole.hr>



description: |

  The PXA1908 clock subsystem generates and supplies clock to various

  controllers within the PXA1908 SoC. The PXA1908 contains numerous clock

  controller blocks, with the ones currently supported being APBC, APBCP, MPMU

  and APMU roughly corresponding to internal buses.



  All these clock identifiers could be found in <include/dt-bindings/marvell,pxa1908.h>.



properties:

  compatible:

    enum:

      - marvell,pxa1908-apbc

      - marvell,pxa1908-apbcp

      - marvell,pxa1908-mpmu

      - marvell,pxa1908-apmu



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  # APMU block:

  - |

    clock-controller@d4282800 {

      compatible = "marvell,pxa1908-apmu";

      reg = <0xd4282800 0x400>;

      #clock-cells = <1>;

    };

Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml

+3 −1
Original line number Diff line number Diff line
@@ -17,7 +17,9 @@ description: | 


properties:

  compatible:

    const: qcom,gcc-sm8450

    enum:

      - qcom,gcc-sm8450

      - qcom,sm8475-gcc



  clocks:

    items:

Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml

+34 −7
Original line number Diff line number Diff line
@@ -4,31 +4,35 @@ 
$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on IPQ5332

title: Qualcomm Global Clock & Reset Controller on IPQ5332 and IPQ5424



maintainers:

  - Bjorn Andersson <andersson@kernel.org>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on IPQ5332.

  domains on IPQ5332 and IPQ5424.



  See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h



allOf:

  - $ref: qcom,gcc.yaml#

  See also:

    include/dt-bindings/clock/qcom,gcc-ipq5332.h

    include/dt-bindings/clock/qcom,gcc-ipq5424.h



properties:

  compatible:

    const: qcom,ipq5332-gcc

    enum:

      - qcom,ipq5332-gcc

      - qcom,ipq5424-gcc



  clocks:

    minItems: 5

    items:

      - description: Board XO clock source

      - description: Sleep clock source

      - description: PCIE 2lane PHY pipe clock source

      - description: PCIE 2lane x1 PHY pipe clock source (For second lane)

      - description: USB PCIE wrapper pipe clock source

      - description: PCIE 2-lane PHY2 pipe clock source

      - description: PCIE 2-lane PHY3 pipe clock source



  '#power-domain-cells': false

  '#interconnect-cells':
@@ -38,6 +42,29 @@ required: 
  - compatible

  - clocks



allOf:

  - $ref: qcom,gcc.yaml#

  - if:

      properties:

        compatible:

          contains:

            const: qcom,ipq5332-gcc

    then:

      properties:

        clocks:

          maxItems: 5



  - if:

      properties:

        compatible:

          contains:

            const: qcom,ipq5424-gcc

    then:

      properties:

        clocks:

          minItems: 7

          maxItems: 7



unevaluatedProperties: false



examples:

Documentation/devicetree/bindings/clock/qcom,qcs8300-gcc.yaml

0 → 100644
+66 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,qcs8300-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Technologies, Inc. Global Clock & Reset Controller on QCS8300



maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Imran Shaik <quic_imrashai@quicinc.com>



description: |

  Qualcomm Technologies, Inc. Global clock control module provides the clocks, resets and

  power domains on QCS8300



  See also: include/dt-bindings/clock/qcom,qcs8300-gcc.h



properties:

  compatible:

    const: qcom,qcs8300-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Sleep clock source

      - description: PCIE 0 Pipe clock source

      - description: PCIE 1 Pipe clock source

      - description: PCIE Phy Auxiliary clock source

      - description: First EMAC controller reference clock

      - description: UFS Phy Rx symbol 0 clock source

      - description: UFS Phy Rx symbol 1 clock source

      - description: UFS Phy Tx symbol 0 clock source

      - description: USB3 Phy wrapper pipe clock source



required:

  - compatible

  - clocks

  - '#power-domain-cells'



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,qcs8300-gcc";

      reg = <0x00100000 0xc7018>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&sleep_clk>,

               <&pcie_0_pipe_clk>,

               <&pcie_1_pipe_clk>,

               <&pcie_phy_aux_clk>,

               <&rxc0_ref_clk>,

               <&ufs_phy_rx_symbol_0_clk>,

               <&ufs_phy_rx_symbol_1_clk>,

               <&ufs_phy_tx_symbol_0_clk>,

               <&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };

...