Commit 0cf32b1f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and... 

Merge branches 'clk-samsung', 'clk-microchip', 'clk-imx', 'clk-amlogic' and 'clk-allwinner' into clk-next

* clk-samsung:
  clk: samsung: Introduce Exynos8895 clock driver
  clk: samsung: clk-pll: Add support for pll_{1051x,1052x}
  dt-bindings: clock: samsung: Add Exynos8895 SoC
  clk: samsung: gs101: make all ufs related clocks critical
  clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support
  dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
  clk: samsung: Fix out-of-bound access of of_match_node()
  dt-bindings: clock: samsung: remove define with number of clocks for FSD
  clk: samsung: fsd: do not define number of clocks in bindings
  clk: samsung: Fix errors reported by checkpatch
  clk: samsung: Fix block comment style warnings reported by checkpatch

* clk-microchip:
  clk: lan966x: add support for lan969x SoC clock driver
  clk: lan966x: prepare driver for lan969x support
  clk: lan966x: make clk_names const char * const
  dt-bindings: clock: add support for lan969x

* clk-imx:
  clk: imx: imx8-acm: Fix return value check in clk_imx_acm_attach_pm_domains()
  clk: imx: lpcg-scu: Skip HDMI LPCG clock save/restore
  clk: imx: clk-scu: fix clk enable state save and restore
  clk: imx: fracn-gppll: fix pll power up
  clk: imx: fracn-gppll: correct PLL initialization flow
  clk: imx: lpcg-scu: SW workaround for errata (e10858)
  clk: imx: add i.MX91 clk
  dt-bindings: clock: Add i.MX91 clock support
  dt-bindings: clock: imx93: Drop IMX93_CLK_END macro definition
  clk: imx93: Move IMX93_CLK_END macro to clk driver
  clk: imx95-blk-ctl: Add one clock gate for HSIO block
  dt-bindings: clock: nxp,imx95-blk-ctl: Add compatible string for i.MX95 HSIO BLK CTRL

* clk-amlogic:
  clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUX
  clk: amlogic: axg-audio: use the auxiliary reset driver
  reset: amlogic: Fix small whitespace issue
  reset: amlogic: add auxiliary reset driver support
  reset: amlogic: split the device core and platform probe
  reset: amlogic: move drivers to a dedicated directory
  reset: amlogic: add reset status support
  reset: amlogic: use reset number instead of register count
  reset: amlogic: add driver parameters
  reset: amlogic: make parameters unsigned
  reset: amlogic: use generic data matching function
  reset: amlogic: convert driver to regmap
  dt-bindings: clock: convert amlogic,meson8b-clkc.txt to dtschema
  clk: meson: meson8b: remove spinlock
  clk: meson: mpll: Delete a useless spinlock from the MPLL
  clk: meson: s4: pll: fix frac maximum value for hifi_pll
  clk: meson: c3: pll: fix frac maximum value for hifi_pll
  clk: meson: Support PLL with fixed fractional denominators
  clk: meson: s4: pll: hifi_pll support fractional multiplier

* clk-allwinner:
  clk: sunxi-ng: Use of_property_present() for non-boolean properties
  clk: sunxi-ng: d1: Fix PLL_AUDIO0 preset
  clk: sunxi-ng: Constify struct ccu_reset_map
  clk: sunxi-ng: h616: Add sigma-delta modulation settings for audio PLL
parents b2f82401 31062ea8 9d0af685 dd8cbf41 681ed497 ea1ba200

Documentation/devicetree/bindings/clock/amlogic,meson8-clkc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/amlogic,meson8-clkc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Controller



maintainers:

  - Neil Armstrong <neil.armstrong@linaro.org>



properties:

  compatible:

    oneOf:

      - enum:

          - amlogic,meson8-clkc

          - amlogic,meson8b-clkc

      - items:

          - const: amlogic,meson8m2-clkc

          - const: amlogic,meson8-clkc



  clocks:

    minItems: 2

    maxItems: 3



  clock-names:

    minItems: 2

    items:

      - const: xtal

      - const: ddr_pll

      - const: clk_32k



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



required:

  - compatible

  - clocks

  - clock-names

  - '#reset-cells'



additionalProperties: false

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt

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* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit



The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and

supplies clock to various controllers within the SoC.



Required Properties:



- compatible: must be one of:

	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs

	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs

	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs

- #clock-cells: should be 1.

- #reset-cells: should be 1.

- clocks: list of clock phandles, one for each entry in clock-names

- clock-names: should contain the following:

  * "xtal": the 24MHz system oscillator

  * "ddr_pll": the DDR PLL clock

  * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN)



Parent node should have the following properties :

- compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon"

- reg: base address and size of the HHI system control register space.



Each clock is assigned an identifier and client nodes can use this identifier

to specify the clock which they consume. All available clocks are defined as

preprocessor macros in the dt-bindings/clock/meson8b-clkc.h header and can be

used in device tree sources.



Similarly a preprocessor macro for each reset line is defined in

dt-bindings/reset/amlogic,meson8b-clkc-reset.h (which can be used from the

device tree sources).





Example: Clock controller node:



	clkc: clock-controller {

		compatible = "amlogic,meson8b-clkc";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};





Example: UART controller node that consumes the clock generated by the clock

  controller:



	uart_AO: serial@c81004c0 {

		compatible = "amlogic,meson-uart";

		reg = <0xc81004c0 0x14>;

		interrupts = <0 90 1>;

		clocks = <&clkc CLKID_CLK81>;

	};

Documentation/devicetree/bindings/clock/imx93-clock.yaml

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@@ -16,6 +16,7 @@ description: | 
properties:

  compatible:

    enum:

      - fsl,imx91-ccm

      - fsl,imx93-ccm



  reg:

Documentation/devicetree/bindings/clock/microchip,lan966x-gck.yaml

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properties:

  compatible:

    const: microchip,lan966x-gck

    oneOf:

      - enum:

          - microchip,lan966x-gck

          - microchip,lan9691-gck

      - items:

          - enum:

              - microchip,lan9698-gck

              - microchip,lan9696-gck

              - microchip,lan9694-gck

              - microchip,lan9693-gck

              - microchip,lan9692-gck

          - const: microchip,lan9691-gck



  reg:

    minItems: 1

Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml

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@@ -13,9 +13,10 @@ properties: 
  compatible:

    items:

      - enum:

          - nxp,imx95-lvds-csr

          - nxp,imx95-display-csr

          - nxp,imx95-camera-csr

          - nxp,imx95-display-csr

          - nxp,imx95-hsio-blk-ctl

          - nxp,imx95-lvds-csr

          - nxp,imx95-netcmix-blk-ctrl

          - nxp,imx95-vpu-csr

      - const: syscon