Commit 3ce2e14a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-rockchip', 'clk-samsung' and 'clk-imx' into clk-next 

* clk-rockchip:
  dt-bindings: reset: fix double id on rk3562-cru reset ids
  clk: rockchip: Add clock controller for the RK3562
  dt-bindings: clock: Add RK3562 cru
  clk: rockchip: rk3528: Add reset lookup table
  clk: rockchip: Add clock controller driver for RK3528 SoC
  clk: rockchip: Add PLL flag ROCKCHIP_PLL_FIXED_MODE
  dt-bindings: clock: Document clock and reset unit of RK3528
  clk: rockchip: rk3328: fix wrong clk_ref_usb3otg parent
  clk: rockchip: rk3568: mark hclk_vi as critical
  clk: rockchip: rk3188: use PCLK_CIF0/1 clock IDs on RK3066
  dt-bindings: clock: rk3188-common: add PCLK_CIF0/PCLK_CIF1

* clk-samsung:
  clk: samsung: Drop unused clk.h and of.h headers
  clk: samsung: Add missing mod_devicetable.h header
  clk: samsung: add initial exynos7870 clock driver
  clk: samsung: introduce Exynos2200 clock driver
  clk: samsung: clk-pll: add support for pll_4311
  dt-bindings: clock: add clock definitions and documentation for exynos7870 CMU
  dt-bindings: clock: add Exynos2200 SoC
  clk: samsung: Fix UBSAN panic in samsung_clk_init()
  clk: samsung: Fix spelling mistake "stablization" -> "stabilization"
  clk: samsung: exynos990: Add CMU_PERIS block
  dt-bindings: clock: exynos990: Add CMU_PERIS block

* clk-imx:
  clk: imx8mp: inform CCF of maximum frequency of clocks
  dt-bindings: clock: imx8m: document nominal/overdrive properties
  clk: clk-imx8mp-audiomix: fix dsp/ocram_a clock parents
  dt-bindings: clock: imx8mp: add axi clock
parents 316f4b91 9d484eac 4defb935 8fbf3d47

Documentation/devicetree/bindings/clock/imx8m-clock.yaml

+8 −0
Original line number Diff line number Diff line
@@ -43,6 +43,13 @@ properties: 
      ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8m-clock.h

      for the full list of i.MX8M clock IDs.



  fsl,operating-mode:

    $ref: /schemas/types.yaml#/definitions/string

    enum: [nominal, overdrive]

    description:

      The operating mode of the SoC. This affects the maximum clock rates that

      can safely be configured by the clock controller.



required:

  - compatible

  - reg
@@ -109,6 +116,7 @@ examples: 
                 <&clk_ext3>, <&clk_ext4>;

        clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",

                      "clk_ext3", "clk_ext4";

        fsl,operating-mode = "nominal";

    };



  - |

Documentation/devicetree/bindings/clock/imx8mp-audiomix.yaml

+6 −4
Original line number Diff line number Diff line
@@ -24,8 +24,8 @@ properties: 
    maxItems: 1



  clocks:

    minItems: 7

    maxItems: 7

    minItems: 8

    maxItems: 8



  clock-names:

    items:
@@ -36,6 +36,7 @@ properties: 
      - const: sai5

      - const: sai6

      - const: sai7

      - const: axi



  '#clock-cells':

    const: 1
@@ -72,10 +73,11 @@ examples: 
                 <&clk IMX8MP_CLK_SAI3>,

                 <&clk IMX8MP_CLK_SAI5>,

                 <&clk IMX8MP_CLK_SAI6>,

                 <&clk IMX8MP_CLK_SAI7>;

                 <&clk IMX8MP_CLK_SAI7>,

                 <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>;

        clock-names = "ahb",

                      "sai1", "sai2", "sai3",

                      "sai5", "sai6", "sai7";

                      "sai5", "sai6", "sai7", "axi";

        power-domains = <&pgc_audio>;

    };

Documentation/devicetree/bindings/clock/rockchip,rk3528-cru.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3528-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip RK3528 Clock and Reset Controller



maintainers:

  - Yao Zi <ziyao@disroot.org>



description: |

  The RK3528 clock controller generates the clock and also implements a reset

  controller for SoC peripherals. For example, it provides SCLK_UART0 and

  PCLK_UART0 as well as SRST_P_UART0 and SRST_S_UART0 for the first UART

  module.

  Each clock is assigned an identifier, consumer nodes can use it to specify

  the clock. All available clock and reset IDs are defined in dt-binding

  headers.



properties:

  compatible:

    const: rockchip,rk3528-cru



  reg:

    maxItems: 1



  clocks:

    items:

      - description: External 24MHz oscillator clock

      - description: >

          50MHz clock generated by PHY module, for generating GMAC0 clocks only.



  clock-names:

    items:

      - const: xin24m

      - const: gmac0



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    clock-controller@ff4a0000 {

        compatible = "rockchip,rk3528-cru";

        reg = <0xff4a0000 0x30000>;

        clocks = <&xin24m>, <&gmac0_clk>;

        clock-names = "xin24m", "gmac0";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/rockchip,rk3562-cru.yaml

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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/rockchip,rk3562-cru.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Rockchip rk3562 Clock and Reset Control Module



maintainers:

  - Elaine Zhang <zhangqing@rock-chips.com>

  - Heiko Stuebner <heiko@sntech.de>



description:

  The RK3562 clock controller generates the clock and also implements a reset

  controller for SoC peripherals. For example it provides SCLK_UART2 and

  PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART

  module.



properties:

  compatible:

    const: rockchip,rk3562-cru



  reg:

    maxItems: 1



  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  clocks:

    maxItems: 2



  clock-names:

    items:

      - const: xin24m

      - const: xin32k



required:

  - compatible

  - reg

  - "#clock-cells"

  - "#reset-cells"



additionalProperties: false



examples:

  - |

    clock-controller@ff100000 {

      compatible = "rockchip,rk3562-cru";

      reg = <0xff100000 0x40000>;

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/samsung,exynos2200-cmu.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/samsung,exynos2200-cmu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung Exynos2200 SoC clock controller



maintainers:

  - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>

  - Chanwoo Choi <cw00.choi@samsung.com>

  - Krzysztof Kozlowski <krzk@kernel.org>



description: |

  Exynos2200 clock controller is comprised of several CMU units, generating

  clocks for different domains. Those CMU units are modeled as separate device

  tree nodes, and might depend on each other. The root clocks in that root tree

  are two external clocks: XTCXO (76.8 MHz) and RTCCLK (32768 Hz). XTCXO must be

  defined as a fixed-rate clock in dts, whereas RTCCLK originates from PMIC.



  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and

  dividers; all other clocks of function blocks (other CMUs) are usually

  derived from CMU_TOP.



  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All clocks available for usage

  in clock consumer nodes are defined as preprocessor macros in

  'include/dt-bindings/clock/samsung,exynos2200-cmu.h' header.



properties:

  compatible:

    enum:

      - samsung,exynos2200-cmu-alive

      - samsung,exynos2200-cmu-cmgp

      - samsung,exynos2200-cmu-hsi0

      - samsung,exynos2200-cmu-peric0

      - samsung,exynos2200-cmu-peric1

      - samsung,exynos2200-cmu-peric2

      - samsung,exynos2200-cmu-peris

      - samsung,exynos2200-cmu-top

      - samsung,exynos2200-cmu-ufs

      - samsung,exynos2200-cmu-vts



  clocks:

    minItems: 1

    maxItems: 6



  clock-names:

    minItems: 1

    maxItems: 6



  "#clock-cells":

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - clocks

  - clock-names

  - reg

  - "#clock-cells"



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos2200-cmu-alive



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (76.8 MHz)

            - description: CMU_ALIVE NOC clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: noc



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos2200-cmu-cmgp



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (76.8 MHz)

            - description: CMU_CMGP NOC clock (from CMU_TOP)

            - description: CMU_CMGP PERI clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: noc

            - const: peri



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos2200-cmu-hsi0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (76.8 MHz)

            - description: External RTC clock (32768 Hz)

            - description: CMU_HSI0 NOC clock (from CMU_TOP)

            - description: CMU_HSI0 DPGTC clock (from CMU_TOP)

            - description: CMU_HSI0 DPOSC clock (from CMU_TOP)

            - description: CMU_HSI0 USB32DRD clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: rtcclk

            - const: noc

            - const: dpgtc

            - const: dposc

            - const: usb



  - if:

      properties:

        compatible:

          contains:

            enum:

              - samsung,exynos2200-cmu-peric0

              - samsung,exynos2200-cmu-peric1

              - samsung,exynos2200-cmu-peric2



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (76.8 MHz)

            - description: CMU_PERICn NOC clock (from CMU_TOP)

            - description: CMU_PERICn IP0 clock (from CMU_TOP)

            - description: CMU_PERICn IP1 clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: noc

            - const: ip0

            - const: ip1



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos2200-cmu-peris



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25.6 MHz)

            - description: CMU_PERIS NOC clock (from CMU_TOP)

            - description: CMU_PERIS GIC clock (from CMU_TOP)



        clock-names:

          items:

            - const: tcxo_div3

            - const: noc

            - const: gic



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos2200-cmu-top



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (76.8 MHz)



        clock-names:

          items:

            - const: oscclk



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos2200-cmu-ufs



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (76.8 MHz)

            - description: CMU_UFS NOC clock (from CMU_TOP)

            - description: CMU_UFS MMC clock (from CMU_TOP)

            - description: CMU_UFS UFS clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: noc

            - const: mmc

            - const: ufs



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos2200-cmu-vts



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (76.8 MHz)

            - description: CMU_VTS DMIC clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dmic



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/samsung,exynos2200-cmu.h>



    cmu_vts: clock-controller@15300000 {

        compatible = "samsung,exynos2200-cmu-vts";

        reg = <0x15300000 0x8000>;

        #clock-cells = <1>;



        clocks = <&oscclk>,

                 <&cmu_top CLK_DOUT_CMU_VTS_DMIC>;

        clock-names = "oscclk", "dmic";

    };



...