Commit 4a35e6fc authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-counted', 'clk-imx', 'clk-amlogic', 'clk-binding' and... 

Merge branches 'clk-counted', 'clk-imx', 'clk-amlogic', 'clk-binding' and 'clk-rockchip' into clk-next

* clk-counted:
  clk: bcm: rpi: Assign ->num before accessing ->hws
  clk: bcm: dvp: Assign ->num before accessing ->hws

* clk-imx:
  clk: imx: imx8mp: Convert to platform remove callback returning void
  clk: imx: imx8mp: Switch to RUNTIME_PM_OPS()
  clk: imx: add i.MX95 BLK CTL clk driver
  dt-bindings: clock: support i.MX95 Display Master CSR module
  dt-bindings: clock: support i.MX95 BLK CTL module
  dt-bindings: clock: add i.MX95 clock header
  clk: imx: imx8mp: Add pm_runtime support for power saving

* clk-amlogic:
  clk: meson: s4: fix module autoloading
  clk: meson: fix module license to GPL only
  clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
  clk: meson: add vclk driver
  clk: meson: pll: print out pll name when unable to lock it
  clk: meson: s4: pll: determine maximum register in regmap config
  clk: meson: s4: peripherals: determine maximum register in regmap config
  clk: meson: a1: pll: determine maximum register in regmap config
  clk: meson: a1: peripherals: determine maximum register in regmap config

* clk-binding:
  dt-bindings: clock: fixed: Define a preferred node name

* clk-rockchip:
  clk: rockchip: rk3568: Add PLL rate for 724 MHz
  clk: rockchip: Remove an unused field in struct rockchip_mmc_clock
  clk: rockchip: rk3588: Add reset line for HDMI Receiver
  clk: rockchip: rk3568: Add missing USB480M_PHY mux
  dt-bindings: reset: Define reset id used for HDMI Receiver
  dt-bindings: clock: rockchip: add USB480M_PHY mux
parents 7552d1b9 6dc445c1 16fb2173 d8555714 b3e99124 2f8acf78

Documentation/devicetree/bindings/clock/fixed-clock.yaml

+9 −0
Original line number Diff line number Diff line
@@ -11,6 +11,15 @@ maintainers: 
  - Stephen Boyd <sboyd@kernel.org>



properties:

  $nodename:

    anyOf:

      - description:

          Preferred name is 'clock-<freq>' with <freq> being the output

          frequency as defined in the 'clock-frequency' property.

        pattern: "^clock-([0-9]+|[a-z0-9-]+)$"

      - description: Any name allowed

        deprecated: true



  compatible:

    const: fixed-clock

Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml

+9 −0
Original line number Diff line number Diff line
@@ -11,6 +11,15 @@ maintainers: 
  - Stephen Boyd <sboyd@kernel.org>



properties:

  $nodename:

    anyOf:

      - description:

          If the frequency is fixed, the preferred name is 'clock-<freq>' with

          <freq> being the output frequency.

        pattern: "^clock-([0-9]+|[0-9a-z-]+)$"

      - description: Any name allowed

        deprecated: true



  compatible:

    enum:

      - fixed-factor-clock

Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml

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+56 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/nxp,imx95-blk-ctl.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX95 Block Control



maintainers:

  - Peng Fan <peng.fan@nxp.com>



properties:

  compatible:

    items:

      - enum:

          - nxp,imx95-lvds-csr

          - nxp,imx95-display-csr

          - nxp,imx95-camera-csr

          - nxp,imx95-vpu-csr

      - const: syscon



  reg:

    maxItems: 1



  power-domains:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 1

    description:

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See

      include/dt-bindings/clock/nxp,imx95-clock.h



required:

  - compatible

  - reg

  - '#clock-cells'

  - power-domains

  - clocks



additionalProperties: false



examples:

  - |

    syscon@4c410000 {

      compatible = "nxp,imx95-vpu-csr", "syscon";

      reg = <0x4c410000 0x10000>;

      #clock-cells = <1>;

      clocks = <&scmi_clk 114>;

      power-domains = <&scmi_devpd 21>;

    };

...

Documentation/devicetree/bindings/clock/nxp,imx95-display-master-csr.yaml

0 → 100644
+64 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/nxp,imx95-display-master-csr.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: NXP i.MX95 Display Master Block Control



maintainers:

  - Peng Fan <peng.fan@nxp.com>



properties:

  compatible:

    items:

      - const: nxp,imx95-display-master-csr

      - const: syscon



  reg:

    maxItems: 1



  power-domains:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 1

    description:

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See

      include/dt-bindings/clock/nxp,imx95-clock.h



  mux-controller:

    type: object

    $ref: /schemas/mux/reg-mux.yaml



required:

  - compatible

  - reg

  - '#clock-cells'

  - mux-controller

  - power-domains

  - clocks



additionalProperties: false



examples:

  - |

    syscon@4c410000 {

      compatible = "nxp,imx95-display-master-csr", "syscon";

      reg = <0x4c410000 0x10000>;

      #clock-cells = <1>;

      clocks = <&scmi_clk 62>;

      power-domains = <&scmi_devpd 3>;



      mux: mux-controller {

        compatible = "mmio-mux";

        #mux-control-cells = <1>;

        mux-reg-masks = <0x4 0x00000001>; /* Pixel_link_sel */

        idle-states = <0>;

      };

    };

...

drivers/clk/bcm/clk-bcm2711-dvp.c

+2 −1
Original line number Diff line number Diff line
@@ -56,6 +56,8 @@ static int clk_dvp_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	data->num = NR_CLOCKS;



	data->hws[0] = clk_hw_register_gate_parent_data(&pdev->dev,

							"hdmi0-108MHz",

							&clk_dvp_parent, 0,
@@ -76,7 +78,6 @@ static int clk_dvp_probe(struct platform_device *pdev) 
		goto unregister_clk0;

	}



	data->num = NR_CLOCKS;

	ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,

				     data);

	if (ret)