Unverified Commit 8397c58e authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-marvell', 'clk-xilinx', 'clk-mediatek' and 'clk-loongson' into clk-next 

 - Add Mediatek MT8196 clk drivers

* clk-marvell:
  clk: mmp: pxa1908: Instantiate power driver through auxiliary bus

* clk-xilinx:
  clk: clocking-wizard: Fix output clock register offset for Versal platforms
  clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()

* clk-mediatek: (31 commits)
  clk: mediatek: Add MT8196 vencsys clock support
  clk: mediatek: Add MT8196 vdecsys clock support
  clk: mediatek: Add MT8196 ovl1 clock support
  clk: mediatek: Add MT8196 ovl0 clock support
  clk: mediatek: Add MT8196 disp-ao clock support
  clk: mediatek: Add MT8196 disp1 clock support
  clk: mediatek: Add MT8196 disp0 clock support
  clk: mediatek: Add MT8196 mfg clock support
  clk: mediatek: Add MT8196 mdpsys clock support
  clk: mediatek: Add MT8196 mcu clock support
  clk: mediatek: Add MT8196 I2C clock support
  clk: mediatek: Add MT8196 pextpsys clock support
  clk: mediatek: Add MT8196 ufssys clock support
  clk: mediatek: Add MT8196 peripheral clock support
  clk: mediatek: Add MT8196 vlpckgen clock support
  clk: mediatek: Add MT8196 topckgen2 clock support
  clk: mediatek: Add MT8196 topckgen clock support
  clk: mediatek: Add MT8196 apmixedsys clock support
  dt-bindings: clock: mediatek: Describe MT8196 clock controllers
  clk: mediatek: clk-mtk: Add MUX_DIV_GATE macro
  ...

* clk-loongson:
  clk: loongson2: Add clock definitions for Loongson-2K0300 SoC
  clk: loongson2: Avoid hardcoding firmware name of the reference clock
  clk: loongson2: Allow zero divisors for dividers
  clk: loongson2: Support scale clocks with an alternative mode
  clk: loongson2: Allow specifying clock flags for gate clock
  dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
parents b91217d9 a787ab59 7c2e86f7 2f66f069 74743c53

Documentation/devicetree/bindings/clock/loongson,ls2k-clk.yaml

+15 −3
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ description: | 
properties:

  compatible:

    enum:

      - loongson,ls2k0300-clk

      - loongson,ls2k0500-clk

      - loongson,ls2k-clk  # This is for Loongson-2K1000

      - loongson,ls2k2000-clk
@@ -24,8 +25,7 @@ properties: 
    maxItems: 1



  clocks:

    items:

      - description: 100m ref

    maxItems: 1



  clock-names:

    items:
@@ -38,11 +38,23 @@ properties: 
      ID in its "clocks" phandle cell. See include/dt-bindings/clock/loongson,ls2k-clk.h

      for the full list of Loongson-2 SoC clock IDs.



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: loongson,ls2k0300-clk

    then:

      properties:

        clock-names: false

    else:

      required:

        - clock-names



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false

Documentation/devicetree/bindings/clock/mediatek,mt8196-clock.yaml

0 → 100644
+112 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Functional Clock Controller for MT8196



maintainers:

  - Guangjie Song <guangjie.song@mediatek.com>

  - Laura Nao <laura.nao@collabora.com>



description: |

  The clock architecture in MediaTek SoCs is structured like below:

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The device nodes provide clock gate control in different IP blocks.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8196-imp-iic-wrap-c

          - mediatek,mt8196-imp-iic-wrap-e

          - mediatek,mt8196-imp-iic-wrap-n

          - mediatek,mt8196-imp-iic-wrap-w

          - mediatek,mt8196-mdpsys0

          - mediatek,mt8196-mdpsys1

          - mediatek,mt8196-pericfg-ao

          - mediatek,mt8196-pextp0cfg-ao

          - mediatek,mt8196-pextp1cfg-ao

          - mediatek,mt8196-ufscfg-ao

          - mediatek,mt8196-vencsys

          - mediatek,mt8196-vencsys-c1

          - mediatek,mt8196-vencsys-c2

          - mediatek,mt8196-vdecsys

          - mediatek,mt8196-vdecsys-soc

          - mediatek,mt8196-vdisp-ao

      - const: syscon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1

    description:

      Reset lines for PEXTP0/1 and UFS blocks.



  mediatek,hardware-voter:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      Phandle to the "Hardware Voter" (HWV), as named in the vendor

      documentation for MT8196/MT6991.



      The HWV is a SoC-internal fixed-function MCU used to collect votes from

      both the Application Processor and other remote processors within the SoC.

      It is intended to transparently enable or disable hardware resources (such

      as power domains or clocks) based on internal vote aggregation handled by

      the MCU's internal state machine.



      However, in practice, this design is incomplete. While the HWV performs

      some internal vote aggregation,software is still required to

      - Manually enable power supplies externally, if present and if required

      - Manually enable parent clocks via direct MMIO writes to clock controllers

      - Enable the FENC after the clock has been ungated via direct MMIO

      writes to clock controllers



      As such, the HWV behaves more like a hardware-managed clock reference

      counter than a true voter. Furthermore, it is not a separate

      controller. It merely serves as an alternative interface to the same

      underlying clock or power controller. Actual control still requires

      direct access to the controller's own MMIO register space, in

      addition to writing to the HWV's MMIO region.



      For this reason, a custom phandle is used here - drivers need to directly

      access the HWV MMIO region in a syscon-like fashion, due to how the

      hardware is wired. This differs from true hardware voting systems, which

      typically do not require custom phandles and rely instead on generic APIs

      (clocks, power domains, interconnects).



      The name "hardware-voter" is retained to match vendor documentation, but

      this should not be reused or misunderstood as a proper voting mechanism.



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    pericfg_ao: clock-controller@16640000 {

        compatible = "mediatek,mt8196-pericfg-ao", "syscon";

        reg = <0x16640000 0x1000>;

        mediatek,hardware-voter = <&scp_hwv>;

        #clock-cells = <1>;

    };

  - |

    pextp0cfg_ao: clock-controller@169b0000 {

        compatible = "mediatek,mt8196-pextp0cfg-ao", "syscon";

        reg = <0x169b0000 0x1000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

    };

Documentation/devicetree/bindings/clock/mediatek,mt8196-sys-clock.yaml

0 → 100644
+107 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek System Clock Controller for MT8196



maintainers:

  - Guangjie Song <guangjie.song@mediatek.com>

  - Laura Nao <laura.nao@collabora.com>



description: |

  The clock architecture in MediaTek SoCs is structured like below:

  PLLs -->

          dividers -->

                      muxes

                           -->

                              clock gate



  The apmixedsys, apmixedsys_gp2, vlpckgen, armpll, ccipll, mfgpll and ptppll

  provide most of the PLLs which are generated from the SoC's 26MHZ crystal oscillator.

  The topckgen, topckgen_gp2 and vlpckgen provide dividers and muxes which

  provide the clock source to other IP blocks.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8196-apmixedsys

          - mediatek,mt8196-armpll-b-pll-ctrl

          - mediatek,mt8196-armpll-bl-pll-ctrl

          - mediatek,mt8196-armpll-ll-pll-ctrl

          - mediatek,mt8196-apmixedsys-gp2

          - mediatek,mt8196-ccipll-pll-ctrl

          - mediatek,mt8196-mfgpll-pll-ctrl

          - mediatek,mt8196-mfgpll-sc0-pll-ctrl

          - mediatek,mt8196-mfgpll-sc1-pll-ctrl

          - mediatek,mt8196-ptppll-pll-ctrl

          - mediatek,mt8196-topckgen

          - mediatek,mt8196-topckgen-gp2

          - mediatek,mt8196-vlpckgen

      - const: syscon



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  mediatek,hardware-voter:

    $ref: /schemas/types.yaml#/definitions/phandle

    description: |

      Phandle to the "Hardware Voter" (HWV), as named in the vendor

      documentation for MT8196/MT6991.



      The HWV is a SoC-internal fixed-function MCU used to collect votes from

      both the Application Processor and other remote processors within the SoC.

      It is intended to transparently enable or disable hardware resources (such

      as power domains or clocks) based on internal vote aggregation handled by

      the MCU's internal state machine.



      However, in practice, this design is incomplete. While the HWV performs

      some internal vote aggregation,software is still required to

      - Manually enable power supplies externally, if present and if required

      - Manually enable parent clocks via direct MMIO writes to clock controllers

      - Enable the FENC after the clock has been ungated via direct MMIO

      writes to clock controllers



      As such, the HWV behaves more like a hardware-managed clock reference

      counter than a true voter. Furthermore, it is not a separate

      controller. It merely serves as an alternative interface to the same

      underlying clock or power controller. Actual control still requires

      direct access to the controller's own MMIO register space, in

      addition to writing to the HWV's MMIO region.



      For this reason, a custom phandle is used here - drivers need to directly

      access the HWV MMIO region in a syscon-like fashion, due to how the

      hardware is wired. This differs from true hardware voting systems, which

      typically do not require custom phandles and rely instead on generic APIs

      (clocks, power domains, interconnects).



      The name "hardware-voter" is retained to match vendor documentation, but

      this should not be reused or misunderstood as a proper voting mechanism.



required:

  - compatible

  - reg

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    apmixedsys_clk: syscon@10000800 {

        compatible = "mediatek,mt8196-apmixedsys", "syscon";

        reg = <0x10000800 0x1000>;

        #clock-cells = <1>;

    };

  - |

    topckgen: syscon@10000000 {

        compatible = "mediatek,mt8196-topckgen", "syscon";

        reg = <0x10000000 0x800>;

        mediatek,hardware-voter = <&scp_hwv>;

        #clock-cells = <1>;

    };

MAINTAINERS

+2 −0
Original line number Diff line number Diff line
@@ -2869,7 +2869,9 @@ ARM/Marvell PXA1908 SOC support 
M:	Duje Mihanović <duje@dujemihanovic.xyz>

L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

S:	Maintained

F:	Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml

F:	arch/arm64/boot/dts/marvell/mmp/

F:	drivers/clk/mmp/Kconfig

F:	drivers/clk/mmp/clk-pxa1908*.c

F:	include/dt-bindings/clock/marvell,pxa1908.h
































drivers/clk/Kconfig



+1
−0






























Original line number
Diff line number
Diff line







@@ -512,6 +512,7 @@ source "drivers/clk/imx/Kconfig"







source "drivers/clk/ingenic/Kconfig"









source "drivers/clk/keystone/Kconfig"









source "drivers/clk/mediatek/Kconfig"









source "drivers/clk/mmp/Kconfig"









source "drivers/clk/meson/Kconfig"









source "drivers/clk/mstar/Kconfig"









source "drivers/clk/microchip/Kconfig"