Unverified Commit b91217d9 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-microchip', 'clk-lookup' and 'clk-st' into clk-next 

 - Speed up clk_core_lookup() by using a hashtable

* clk-microchip:
  ARM: at91: remove default values for PMC_PLL_ACR
  clk: at91: add ACR in all PLL settings
  clk: at91: sam9x7: Add peripheral clock id for pmecc
  clk: at91: clk-master: Add check for divide by 3
  clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register
  ARM: at91: pm: save and restore ACR during PLL disable/enable

* clk-lookup:
  clk: Use hashtable for global clk lookups
  clk: Sort include statements

* clk-st:
  dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings
  clk: stm32: introduce clocks for STM32MP21 platform
  dt-bindings: stm32: add STM32MP21 clocks and reset bindings
parents f0fd2482 1803012a 4bf2d274 09976070

Documentation/devicetree/bindings/clock/st,stm32mp21-rcc.yaml

0 → 100644
+199 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/st,stm32mp21-rcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: STM32MP21 Reset Clock Controller



maintainers:

  - Gabriel Fernandez <gabriel.fernandez@foss.st.com>



description: |

  The RCC hardware block is both a reset and a clock controller.

  RCC makes also power management (resume/suspend).



  See also:

    include/dt-bindings/clock/st,stm32mp21-rcc.h

    include/dt-bindings/reset/st,stm32mp21-rcc.h



properties:

  compatible:

    enum:

      - st,stm32mp21-rcc



  reg:

    maxItems: 1



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  clocks:

    items:

      - description: CK_SCMI_HSE High Speed External oscillator (8 to 48 MHz)

      - description: CK_SCMI_HSI High Speed Internal oscillator (~ 64 MHz)

      - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)

      - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)

      - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)

      - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)

      - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock

      - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock

      - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock

      - description: CK_SCMI_ICN_DDR DDR interconnect bus clock

      - description: CK_SCMI_ICN_DISPLAY Display interconnect bus clock

      - description: CK_SCMI_ICN_HSL HSL interconnect bus clock

      - description: CK_SCMI_ICN_NIC NIC interconnect bus clock

      - description: CK_SCMI_FLEXGEN_07 flexgen clock 7

      - description: CK_SCMI_FLEXGEN_08 flexgen clock 8

      - description: CK_SCMI_FLEXGEN_09 flexgen clock 9

      - description: CK_SCMI_FLEXGEN_10 flexgen clock 10

      - description: CK_SCMI_FLEXGEN_11 flexgen clock 11

      - description: CK_SCMI_FLEXGEN_12 flexgen clock 12

      - description: CK_SCMI_FLEXGEN_13 flexgen clock 13

      - description: CK_SCMI_FLEXGEN_14 flexgen clock 14

      - description: CK_SCMI_FLEXGEN_16 flexgen clock 16

      - description: CK_SCMI_FLEXGEN_17 flexgen clock 17

      - description: CK_SCMI_FLEXGEN_18 flexgen clock 18

      - description: CK_SCMI_FLEXGEN_19 flexgen clock 19

      - description: CK_SCMI_FLEXGEN_20 flexgen clock 20

      - description: CK_SCMI_FLEXGEN_21 flexgen clock 21

      - description: CK_SCMI_FLEXGEN_22 flexgen clock 22

      - description: CK_SCMI_FLEXGEN_23 flexgen clock 23

      - description: CK_SCMI_FLEXGEN_24 flexgen clock 24

      - description: CK_SCMI_FLEXGEN_25 flexgen clock 25

      - description: CK_SCMI_FLEXGEN_26 flexgen clock 26

      - description: CK_SCMI_FLEXGEN_27 flexgen clock 27

      - description: CK_SCMI_FLEXGEN_29 flexgen clock 29

      - description: CK_SCMI_FLEXGEN_30 flexgen clock 30

      - description: CK_SCMI_FLEXGEN_31 flexgen clock 31

      - description: CK_SCMI_FLEXGEN_33 flexgen clock 33

      - description: CK_SCMI_FLEXGEN_36 flexgen clock 36

      - description: CK_SCMI_FLEXGEN_37 flexgen clock 37

      - description: CK_SCMI_FLEXGEN_38 flexgen clock 38

      - description: CK_SCMI_FLEXGEN_39 flexgen clock 39

      - description: CK_SCMI_FLEXGEN_40 flexgen clock 40

      - description: CK_SCMI_FLEXGEN_41 flexgen clock 41

      - description: CK_SCMI_FLEXGEN_42 flexgen clock 42

      - description: CK_SCMI_FLEXGEN_43 flexgen clock 43

      - description: CK_SCMI_FLEXGEN_44 flexgen clock 44

      - description: CK_SCMI_FLEXGEN_45 flexgen clock 45

      - description: CK_SCMI_FLEXGEN_46 flexgen clock 46

      - description: CK_SCMI_FLEXGEN_47 flexgen clock 47

      - description: CK_SCMI_FLEXGEN_48 flexgen clock 48

      - description: CK_SCMI_FLEXGEN_50 flexgen clock 50

      - description: CK_SCMI_FLEXGEN_51 flexgen clock 51

      - description: CK_SCMI_FLEXGEN_52 flexgen clock 52

      - description: CK_SCMI_FLEXGEN_53 flexgen clock 53

      - description: CK_SCMI_FLEXGEN_54 flexgen clock 54

      - description: CK_SCMI_FLEXGEN_55 flexgen clock 55

      - description: CK_SCMI_FLEXGEN_56 flexgen clock 56

      - description: CK_SCMI_FLEXGEN_57 flexgen clock 57

      - description: CK_SCMI_FLEXGEN_58 flexgen clock 58

      - description: CK_SCMI_FLEXGEN_61 flexgen clock 61

      - description: CK_SCMI_FLEXGEN_62 flexgen clock 62

      - description: CK_SCMI_FLEXGEN_63 flexgen clock 63

      - description: CK_SCMI_ICN_APB1 Peripheral bridge 1

      - description: CK_SCMI_ICN_APB2 Peripheral bridge 2

      - description: CK_SCMI_ICN_APB3 Peripheral bridge 3

      - description: CK_SCMI_ICN_APB4 Peripheral bridge 4

      - description: CK_SCMI_ICN_APB5 Peripheral bridge 5

      - description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug

      - description: CK_SCMI_TIMG1 Peripheral bridge for timer1

      - description: CK_SCMI_TIMG2 Peripheral bridge for timer2



  access-controllers:

    maxItems: 1



required:

  - compatible

  - reg

  - '#clock-cells'

  - '#reset-cells'

  - clocks



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/st,stm32mp21-rcc.h>



    clock-controller@44200000 {

        compatible = "st,stm32mp21-rcc";

        reg = <0x44200000 0x10000>;

        #clock-cells = <1>;

        #reset-cells = <1>;

        clocks =  <&scmi_clk CK_SCMI_HSE>,

                  <&scmi_clk CK_SCMI_HSI>,

                  <&scmi_clk CK_SCMI_MSI>,

                  <&scmi_clk CK_SCMI_LSE>,

                  <&scmi_clk CK_SCMI_LSI>,

                  <&scmi_clk CK_SCMI_HSE_DIV2>,

                  <&scmi_clk CK_SCMI_ICN_HS_MCU>,

                  <&scmi_clk CK_SCMI_ICN_LS_MCU>,

                  <&scmi_clk CK_SCMI_ICN_SDMMC>,

                  <&scmi_clk CK_SCMI_ICN_DDR>,

                  <&scmi_clk CK_SCMI_ICN_DISPLAY>,

                  <&scmi_clk CK_SCMI_ICN_HSL>,

                  <&scmi_clk CK_SCMI_ICN_NIC>,

                  <&scmi_clk CK_SCMI_FLEXGEN_07>,

                  <&scmi_clk CK_SCMI_FLEXGEN_08>,

                  <&scmi_clk CK_SCMI_FLEXGEN_09>,

                  <&scmi_clk CK_SCMI_FLEXGEN_10>,

                  <&scmi_clk CK_SCMI_FLEXGEN_11>,

                  <&scmi_clk CK_SCMI_FLEXGEN_12>,

                  <&scmi_clk CK_SCMI_FLEXGEN_13>,

                  <&scmi_clk CK_SCMI_FLEXGEN_14>,

                  <&scmi_clk CK_SCMI_FLEXGEN_16>,

                  <&scmi_clk CK_SCMI_FLEXGEN_17>,

                  <&scmi_clk CK_SCMI_FLEXGEN_18>,

                  <&scmi_clk CK_SCMI_FLEXGEN_19>,

                  <&scmi_clk CK_SCMI_FLEXGEN_20>,

                  <&scmi_clk CK_SCMI_FLEXGEN_21>,

                  <&scmi_clk CK_SCMI_FLEXGEN_22>,

                  <&scmi_clk CK_SCMI_FLEXGEN_23>,

                  <&scmi_clk CK_SCMI_FLEXGEN_24>,

                  <&scmi_clk CK_SCMI_FLEXGEN_25>,

                  <&scmi_clk CK_SCMI_FLEXGEN_26>,

                  <&scmi_clk CK_SCMI_FLEXGEN_27>,

                  <&scmi_clk CK_SCMI_FLEXGEN_29>,

                  <&scmi_clk CK_SCMI_FLEXGEN_30>,

                  <&scmi_clk CK_SCMI_FLEXGEN_31>,

                  <&scmi_clk CK_SCMI_FLEXGEN_33>,

                  <&scmi_clk CK_SCMI_FLEXGEN_36>,

                  <&scmi_clk CK_SCMI_FLEXGEN_37>,

                  <&scmi_clk CK_SCMI_FLEXGEN_38>,

                  <&scmi_clk CK_SCMI_FLEXGEN_39>,

                  <&scmi_clk CK_SCMI_FLEXGEN_40>,

                  <&scmi_clk CK_SCMI_FLEXGEN_41>,

                  <&scmi_clk CK_SCMI_FLEXGEN_42>,

                  <&scmi_clk CK_SCMI_FLEXGEN_43>,

                  <&scmi_clk CK_SCMI_FLEXGEN_44>,

                  <&scmi_clk CK_SCMI_FLEXGEN_45>,

                  <&scmi_clk CK_SCMI_FLEXGEN_46>,

                  <&scmi_clk CK_SCMI_FLEXGEN_47>,

                  <&scmi_clk CK_SCMI_FLEXGEN_48>,

                  <&scmi_clk CK_SCMI_FLEXGEN_50>,

                  <&scmi_clk CK_SCMI_FLEXGEN_51>,

                  <&scmi_clk CK_SCMI_FLEXGEN_52>,

                  <&scmi_clk CK_SCMI_FLEXGEN_53>,

                  <&scmi_clk CK_SCMI_FLEXGEN_54>,

                  <&scmi_clk CK_SCMI_FLEXGEN_55>,

                  <&scmi_clk CK_SCMI_FLEXGEN_56>,

                  <&scmi_clk CK_SCMI_FLEXGEN_57>,

                  <&scmi_clk CK_SCMI_FLEXGEN_58>,

                  <&scmi_clk CK_SCMI_FLEXGEN_61>,

                  <&scmi_clk CK_SCMI_FLEXGEN_62>,

                  <&scmi_clk CK_SCMI_FLEXGEN_63>,

                  <&scmi_clk CK_SCMI_ICN_APB1>,

                  <&scmi_clk CK_SCMI_ICN_APB2>,

                  <&scmi_clk CK_SCMI_ICN_APB3>,

                  <&scmi_clk CK_SCMI_ICN_APB4>,

                  <&scmi_clk CK_SCMI_ICN_APB5>,

                  <&scmi_clk CK_SCMI_ICN_APBDBG>,

                  <&scmi_clk CK_SCMI_TIMG1>,

                  <&scmi_clk CK_SCMI_TIMG2>;

    };

...

Documentation/devicetree/bindings/clock/st,stm32mp25-rcc.yaml

+6 −7
Original line number Diff line number Diff line
@@ -11,9 +11,9 @@ maintainers: 


description: |

  The RCC hardware block is both a reset and a clock controller.

  RCC makes also power management (resume/supend).

  RCC makes also power management (resume/suspend).



  See also::

  See also:

    include/dt-bindings/clock/st,stm32mp25-rcc.h

    include/dt-bindings/reset/st,stm32mp25-rcc.h
@@ -38,7 +38,7 @@ properties: 
      - description: CK_SCMI_MSI Low Power Internal oscillator (~ 4 MHz or ~ 16 MHz)

      - description: CK_SCMI_LSE Low Speed External oscillator (32 KHz)

      - description: CK_SCMI_LSI Low Speed Internal oscillator (~ 32 KHz)

      - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (coud be gated)

      - description: CK_SCMI_HSE_DIV2 CK_SCMI_HSE divided by 2 (could be gated)

      - description: CK_SCMI_ICN_HS_MCU High Speed interconnect bus clock

      - description: CK_SCMI_ICN_LS_MCU Low Speed interconnect bus clock

      - description: CK_SCMI_ICN_SDMMC SDMMC interconnect bus clock
@@ -108,15 +108,14 @@ properties: 
      - description: CK_SCMI_ICN_APB2 Peripheral bridge 2

      - description: CK_SCMI_ICN_APB3 Peripheral bridge 3

      - description: CK_SCMI_ICN_APB4 Peripheral bridge 4

      - description: CK_SCMI_ICN_APBDBG Peripheral bridge for degub

      - description: CK_SCMI_ICN_APBDBG Peripheral bridge for debug

      - description: CK_SCMI_TIMG1 Peripheral bridge for timer1

      - description: CK_SCMI_TIMG2 Peripheral bridge for timer2

      - description: CK_SCMI_PLL3 PLL3 clock

      - description: clk_dsi_txbyte DSI byte clock



  access-controllers:

    minItems: 1

    maxItems: 2

    maxItems: 1



required:

  - compatible
@@ -131,7 +130,7 @@ examples: 
  - |

    #include <dt-bindings/clock/st,stm32mp25-rcc.h>



    rcc: clock-controller@44200000 {

    clock-controller@44200000 {

        compatible = "st,stm32mp25-rcc";

        reg = <0x44200000 0x10000>;

        #clock-cells = <1>;

arch/arm/mach-at91/pm_suspend.S

+7 −1
Original line number Diff line number Diff line
@@ -689,6 +689,10 @@ sr_dis_exit: 
	bic	tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID

	str	tmp2, [pmc, #AT91_PMC_PLL_UPDT]



	/* save acr */

	ldr	tmp2, [pmc, #AT91_PMC_PLL_ACR]

	str	tmp2, .saved_acr



	/* save div. */

	mov	tmp1, #0

	ldr	tmp2, [pmc, #AT91_PMC_PLL_CTRL0]
@@ -758,7 +762,7 @@ sr_dis_exit: 
	str	tmp1, [pmc, #AT91_PMC_PLL_UPDT]



	/* step 2. */

	ldr	tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA

	ldr	tmp1, .saved_acr

	str	tmp1, [pmc, #AT91_PMC_PLL_ACR]



	/* step 3. */
@@ -1207,6 +1211,8 @@ ENDPROC(at91_pm_suspend_in_sram) 
#endif

.saved_mckr:

	.word 0

.saved_acr:

	.word 0

.saved_pllar:

	.word 0

.saved_sam9_lpr:

drivers/clk/at91/clk-master.c

+3 −0
Original line number Diff line number Diff line
@@ -580,6 +580,9 @@ clk_sama7g5_master_recalc_rate(struct clk_hw *hw, 
{

	struct clk_master *master = to_clk_master(hw);



	if (master->div == MASTER_PRES_MAX)

		return DIV_ROUND_CLOSEST_ULL(parent_rate, 3);



	return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));

}

drivers/clk/at91/clk-sam9x60-pll.c

+41 −41
Original line number Diff line number Diff line
@@ -93,7 +93,7 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) 


	spin_lock_irqsave(core->lock, flags);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_ID_MSK, core->id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);

	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
@@ -103,11 +103,8 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) 
	    (cmul == frac->mul && cfrac == frac->frac))

		goto unlock;



	/* Recommended value for PMC_PLL_ACR */

	if (core->characteristics->upll)

		val = AT91_PMC_PLL_ACR_DEFAULT_UPLL;

	else

		val = AT91_PMC_PLL_ACR_DEFAULT_PLLA;

	/* Load recommended value for PMC_PLL_ACR */

	val = core->characteristics->acr;

	regmap_write(regmap, AT91_PMC_PLL_ACR, val);



	regmap_write(regmap, AT91_PMC_PLL_CTRL1,
@@ -128,7 +125,7 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) 
		udelay(10);

	}



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -136,7 +133,7 @@ static int sam9x60_frac_pll_set(struct sam9x60_pll_core *core) 
			   AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL,

			   AT91_PMC_PLL_CTRL0_ENLOCK | AT91_PMC_PLL_CTRL0_ENPLL);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -164,7 +161,7 @@ static void sam9x60_frac_pll_unprepare(struct clk_hw *hw) 


	spin_lock_irqsave(core->lock, flags);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_ID_MSK, core->id);



	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0, AT91_PMC_PLL_CTRL0_ENPLL, 0);
@@ -173,7 +170,7 @@ static void sam9x60_frac_pll_unprepare(struct clk_hw *hw) 
		regmap_update_bits(regmap, AT91_PMC_PLL_ACR,

				   AT91_PMC_PLL_ACR_UTMIBG | AT91_PMC_PLL_ACR_UTMIVR, 0);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -262,7 +259,7 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, 


	spin_lock_irqsave(core->lock, irqflags);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

			  core->id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL1, &val);

	cmul = (val & core->layout->mul_mask) >> core->layout->mul_shift;
@@ -275,7 +272,7 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, 
		     (frac->mul << core->layout->mul_shift) |

		     (frac->frac << core->layout->frac_shift));



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -284,7 +281,7 @@ static int sam9x60_frac_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, 
			   AT91_PMC_PLL_CTRL0_ENLOCK |

			   AT91_PMC_PLL_CTRL0_ENPLL);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -338,7 +335,10 @@ static const struct clk_ops sam9x60_frac_pll_ops_chg = { 
	.restore_context = sam9x60_frac_pll_restore_context,

};



/* This function should be called with spinlock acquired. */

/* This function should be called with spinlock acquired.

 * Warning: this function must be called only if the same PLL ID was set in

 *          PLL_UPDT register previously.

 */

static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div,

				    bool enable)

{
@@ -350,7 +350,7 @@ static void sam9x60_div_pll_set_div(struct sam9x60_pll_core *core, u32 div, 
			   core->layout->div_mask | ena_msk,

			   (div << core->layout->div_shift) | ena_val);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -366,7 +366,7 @@ static int sam9x60_div_pll_set(struct sam9x60_pll_core *core) 
	unsigned int val, cdiv;



	spin_lock_irqsave(core->lock, flags);

	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_ID_MSK, core->id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);

	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
@@ -398,13 +398,13 @@ static void sam9x60_div_pll_unprepare(struct clk_hw *hw) 


	spin_lock_irqsave(core->lock, flags);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_ID_MSK, core->id);



	regmap_update_bits(regmap, AT91_PMC_PLL_CTRL0,

			   core->layout->endiv_mask, 0);



	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT,

			  AT91_PMC_PLL_UPDT_UPDATE | AT91_PMC_PLL_UPDT_ID_MSK,

			  AT91_PMC_PLL_UPDT_UPDATE | core->id);
@@ -518,7 +518,7 @@ static int sam9x60_div_pll_set_rate_chg(struct clk_hw *hw, unsigned long rate, 
	div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;



	spin_lock_irqsave(core->lock, irqflags);

	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

			  core->id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);

	cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
@@ -574,7 +574,7 @@ static int sam9x60_div_pll_notifier_fn(struct notifier_block *notifier, 
	div->div = div->safe_div;



	spin_lock_irqsave(core.lock, irqflags);

	regmap_update_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

	regmap_write_bits(regmap, AT91_PMC_PLL_UPDT, AT91_PMC_PLL_UPDT_ID_MSK,

			  core.id);

	regmap_read(regmap, AT91_PMC_PLL_CTRL0, &val);

	cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;