Unverified Commit e3abdd18 authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner'...

Merge branches 'clk-renesas', 'clk-samsung', 'clk-spacemit', 'clk-allwinner' and 'clk-amlogic' into clk-next

* clk-renesas: (42 commits)
  clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well
  clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs
  clk: renesas: r9a09g057: Add XSPI clock/reset
  clk: renesas: r9a09g056: Add XSPI clock/reset
  clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting
  clk: renesas: r9a09g057: Add support for xspi mux and divider
  clk: renesas: r9a09g056: Add support for xspi mux and divider
  clk: renesas: r9a09g077: Add RIIC module clocks
  clk: renesas: r9a09g077: Add PLL2 and SDHI clock support
  clk: renesas: rzv2h: Drop redundant base pointer from pll_clk
  clk: renesas: r9a09g057: Add entries for the RSPIs
  dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID
  dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
  clk: renesas: rzv2h: Add missing include file
  clk: renesas: rzv2h: Use devm_kmemdup_array()
  clk: renesas: Add CPG/MSSR support to RZ/N2H SoC
  clk: renesas: r9a09g077: Add PCLKL core clock
  dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H support
  dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoC
  dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock ID
  ...

* clk-samsung:
  clk: samsung: exynosautov920: add block hsi2 clock support
  dt-bindings: clock: exynosautov920: add hsi2 clock definitions
  dt-bindings: clock: exynosautov920: sort clock definitions
  clk: samsung: exynos850: fix a comment
  clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clock
  clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSD

* clk-spacemit:
  clk: spacemit: ccu_pll: fix error return value in recalc_rate callback
  reset: spacemit: add support for SpacemiT CCU resets
  clk: spacemit: mark K1 pll1_d8 as critical
  clk: spacemit: define three reset-only CCUs
  clk: spacemit: set up reset auxiliary devices
  soc: spacemit: create a header for clock/reset registers
  dt-bindings: soc: spacemit: define spacemit,k1-ccu resets

* clk-allwinner:
  clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()
  clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()
  clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()
  clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()
  clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pll
  clk: sunxi-ng: v3s: Fix de clock definition
  clk: sunxi-ng: sun55i-a523-r-ccu: Add missing PPU0 reset
  dt-bindings: reset: sun55i-a523-r-ccu: Add missing PPU0 reset

* clk-amlogic:
  clk: amlogic: s4: remove unused data
  clk: amlogic: drop clk_regmap tables
  clk: amlogic: get regmap with clk_regmap_init
  clk: amlogic: remove unnecessary headers
  clk: amlogic: axg-audio: use the auxiliary reset driver
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+38 −11
Original line number Diff line number Diff line
@@ -52,9 +52,16 @@ properties:
      - renesas,r8a779f0-cpg-mssr # R-Car S4-8
      - renesas,r8a779g0-cpg-mssr # R-Car V4H
      - renesas,r8a779h0-cpg-mssr # R-Car V4M
      - renesas,r9a09g077-cpg-mssr # RZ/T2H
      - renesas,r9a09g087-cpg-mssr # RZ/N2H

  reg:
    maxItems: 1
    minItems: 1
    items:
      - description: base address of register block 0
      - description: base address of register block 1
    description: base addresses of clock controller. Some controllers
      (like r9a09g077) use two blocks instead of a single one.

  clocks:
    minItems: 1
@@ -92,7 +99,35 @@ properties:
      the datasheet.
    const: 1

if:

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'

allOf:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - renesas,r9a09g077-cpg-mssr
              - renesas,r9a09g087-cpg-mssr
    then:
      properties:
        reg:
          minItems: 2
        clock-names:
          items:
            - const: extal
    else:
      properties:
        reg:
          maxItems: 1
  - if:
      not:
        properties:
          compatible:
@@ -103,14 +138,6 @@ then:
      required:
        - '#reset-cells'

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - '#clock-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
+1 −17
Original line number Diff line number Diff line
@@ -57,8 +57,7 @@ properties:
      can be power-managed through Module Standby should refer to the CPG device
      node in their "power-domains" property, as documented by the generic PM
      Domain bindings in Documentation/devicetree/bindings/power/power-domain.yaml.
      The power domain specifiers defined in <dt-bindings/clock/r9a0*-cpg.h> could
      be used to reference individual CPG power domains.
    const: 0

  '#reset-cells':
    description:
@@ -77,21 +76,6 @@ required:

additionalProperties: false

allOf:
  - if:
      properties:
        compatible:
          contains:
            const: renesas,r9a08g045-cpg
    then:
      properties:
        '#power-domain-cells':
          const: 1
    else:
      properties:
        '#power-domain-cells':
          const: 0

examples:
  - |
    cpg: clock-controller@11010000 {
+31 −6
Original line number Diff line number Diff line
@@ -32,23 +32,24 @@ description: |
properties:
  compatible:
    enum:
      - samsung,exynosautov920-cmu-top
      - samsung,exynosautov920-cmu-cpucl0
      - samsung,exynosautov920-cmu-cpucl1
      - samsung,exynosautov920-cmu-cpucl2
      - samsung,exynosautov920-cmu-peric0
      - samsung,exynosautov920-cmu-peric1
      - samsung,exynosautov920-cmu-misc
      - samsung,exynosautov920-cmu-hsi0
      - samsung,exynosautov920-cmu-hsi1
      - samsung,exynosautov920-cmu-hsi2
      - samsung,exynosautov920-cmu-misc
      - samsung,exynosautov920-cmu-peric0
      - samsung,exynosautov920-cmu-peric1
      - samsung,exynosautov920-cmu-top

  clocks:
    minItems: 1
    maxItems: 4
    maxItems: 5

  clock-names:
    minItems: 1
    maxItems: 4
    maxItems: 5

  "#clock-cells":
    const: 1
@@ -201,6 +202,30 @@ allOf:
            - const: usbdrd
            - const: mmc_card

  - if:
      properties:
        compatible:
          contains:
            const: samsung,exynosautov920-cmu-hsi2

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (38.4 MHz)
            - description: CMU_HSI2 NOC clock (from CMU_TOP)
            - description: CMU_HSI2 NOC UFS clock (from CMU_TOP)
            - description: CMU_HSI2 UFS EMBD clock (from CMU_TOP)
            - description: CMU_HSI2 ETHERNET clock (from CMU_TOP)

        clock-names:
          items:
            - const: oscclk
            - const: noc
            - const: ufs
            - const: embd
            - const: ethernet

required:
  - compatible
  - "#clock-cells"
+10 −0
Original line number Diff line number Diff line
@@ -602,6 +602,16 @@ properties:
              - renesas,r9a09g077m44 # RZ/T2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
          - const: renesas,r9a09g077

      - description: RZ/N2H (R9A09G087)
        items:
          - enum:
              - renesas,rzn2h-evk # RZ/N2H Evaluation Board (RTK9RZN2H0S00000BJ)
          - enum:
              - renesas,r9a09g087m04 # RZ/N2H with Single Cortex-A55 + Dual Cortex-R52 - no security
              - renesas,r9a09g087m24 # RZ/N2H with Dual Cortex-A55 + Dual Cortex-R52 - no security
              - renesas,r9a09g087m44 # RZ/N2H with Quad Cortex-A55 + Dual Cortex-R52 - no security
          - const: renesas,r9a09g087

additionalProperties: true

...
+21 −6
Original line number Diff line number Diff line
@@ -19,6 +19,9 @@ properties:
      - spacemit,k1-syscon-apbc
      - spacemit,k1-syscon-apmu
      - spacemit,k1-syscon-mpmu
      - spacemit,k1-syscon-rcpu
      - spacemit,k1-syscon-rcpu2
      - spacemit,k1-syscon-apbc2

  reg:
    maxItems: 1
@@ -47,9 +50,6 @@ properties:
required:
  - compatible
  - reg
  - clocks
  - clock-names
  - "#clock-cells"
  - "#reset-cells"

allOf:
@@ -57,13 +57,28 @@ allOf:
      properties:
        compatible:
          contains:
            const: spacemit,k1-syscon-apbc
            enum:
              - spacemit,k1-syscon-apmu
              - spacemit,k1-syscon-mpmu
    then:
      required:
        - "#power-domain-cells"
    else:
      properties:
        "#power-domain-cells": false
    else:
  - if:
      properties:
        compatible:
          contains:
            enum:
              - spacemit,k1-syscon-apbc
              - spacemit,k1-syscon-apmu
              - spacemit,k1-syscon-mpmu
    then:
      required:
        - "#power-domain-cells"
        - clocks
        - clock-names
        - "#clock-cells"

additionalProperties: false

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