Commit e988adcb authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-allwinner', 'clk-amlogic' and 'clk-qcom' into clk-next 

* clk-allwinner:
  clk: sunxi-ng: add support for the A523/T527 PRCM CCU
  clk: sunxi-ng: a523: add reset lines
  clk: sunxi-ng: a523: add bus clock gates
  clk: sunxi-ng: a523: remaining mod clocks
  clk: sunxi-ng: a523: add USB mod clocks
  clk: sunxi-ng: a523: add interface mod clocks
  clk: sunxi-ng: a523: add system mod clocks
  clk: sunxi-ng: a523: add video mod clocks
  clk: sunxi-ng: a523: Add support for bus clocks
  clk: sunxi-ng: Add support for the A523/T527 CCU PLLs
  dt-bindings: clk: sunxi-ng: document two Allwinner A523 CCUs
  clk: sunxi-ng: Add support for update bit
  clk: sunxi-ng: mp: provide wrappers for setting feature flags
  clk: sunxi-ng: mp: introduce dual-divider clock
  clk: sunxi-ng: h616: Reparent GPU clock during frequency changes
  clk: sunxi-ng: h616: Add clock/reset for LCD TCON
  dt-bindings: clock: sun50i-h616-ccu: Add LCD TCON clk and reset

* clk-amlogic:
  clk: amlogic: a1: fix a typo
  clk: amlogic: gxbb: drop non existing 32k clock parent
  clk: amlogic: gxbb: drop incorrect flag on 32k clock
  clk: amlogic: g12b: fix cluster A parent data
  clk: amlogic: g12a: fix mmc A peripheral clock

* clk-qcom: (41 commits)
  clk: qcom: Add NSS clock Controller driver for IPQ9574
  clk: qcom: gcc-ipq9574: Add support for gpll0_out_aux clock
  dt-bindings: clock: Add ipq9574 NSSCC clock and reset definitions
  dt-bindings: clock: gcc-ipq9574: Add definition for GPLL0_OUT_AUX
  clk: qcom: gcc-msm8953: fix stuck venus0_core0 clock
  clk: qcom: mmcc-sdm660: fix stuck video_subcore0 clock
  dt-bindings: clock: qcom,x1e80100-camcc: Fix the list of required-opps
  drivers: clk: qcom: ipq5424: fix the freq table of sdcc1_apps clock
  clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490
  dt-bindings: clock: qcom: Add compatible for QCM6490 boards
  clk: qcom: gdsc: Update the status poll timeout for GDSC
  clk: qcom: gdsc: Set retain_ff before moving to HW CTRL
  clk: qcom: gcc-sm8650: Do not turn off USB GDSCs during gdsc_disable()
  clk: qcom: videocc: Constify 'struct qcom_cc_desc'
  clk: qcom: gpucc: Constify 'struct qcom_cc_desc'
  clk: qcom: dispcc: Constify 'struct qcom_cc_desc'
  clk: qcom: camcc: Constify 'struct qcom_cc_desc'
  dt-bindings: clock: qcom: sm8450-camcc: Remove qcom,x1e80100-camcc leftover
  clk: qcom: Add support for Video Clock Controller on QCS8300
  clk: qcom: Add support for GPU Clock Controller on QCS8300
  ...
parents 3ce2e14a 054b4eae 0a1f6dd7 f00618a3

Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/allwinner,sun55i-a523-ccu.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Allwinner A523 Clock Control Unit



maintainers:

  - Andre Przywara <andre.przywara@arm.com>



properties:

  "#clock-cells":

    const: 1



  "#reset-cells":

    const: 1



  compatible:

    enum:

      - allwinner,sun55i-a523-ccu

      - allwinner,sun55i-a523-r-ccu



  reg:

    maxItems: 1



  clocks:

    minItems: 4

    maxItems: 5



  clock-names:

    minItems: 4

    maxItems: 5



required:

  - "#clock-cells"

  - "#reset-cells"

  - compatible

  - reg

  - clocks

  - clock-names



allOf:

  - if:

      properties:

        compatible:

          enum:

            - allwinner,sun55i-a523-ccu



    then:

      properties:

        clocks:

          items:

            - description: High Frequency Oscillator (usually at 24MHz)

            - description: Low Frequency Oscillator (usually at 32kHz)

            - description: Internal Oscillator

            - description: Low Frequency Oscillator fanout



        clock-names:

          items:

            - const: hosc

            - const: losc

            - const: iosc

            - const: losc-fanout



  - if:

      properties:

        compatible:

          enum:

            - allwinner,sun55i-a523-r-ccu



    then:

      properties:

        clocks:

          items:

            - description: High Frequency Oscillator (usually at 24MHz)

            - description: Low Frequency Oscillator (usually at 32kHz)

            - description: Internal Oscillator

            - description: Peripherals PLL

            - description: Audio PLL



        clock-names:

          items:

            - const: hosc

            - const: losc

            - const: iosc

            - const: pll-periph

            - const: pll-audio



additionalProperties: false



examples:

  - |

    clock-controller@2001000 {

        compatible = "allwinner,sun55i-a523-ccu";

        reg = <0x02001000 0x1000>;

        clocks = <&osc24M>, <&osc32k>, <&iosc>, <&r_ccu 1>;

        clock-names = "hosc", "losc", "iosc", "losc-fanout";

        #clock-cells = <1>;

        #reset-cells = <1>;

    };



...

Documentation/devicetree/bindings/clock/qcom,gpucc.yaml

+3 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ title: Qualcomm Graphics Clock & Reset Controller 


maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Imran Shaik <quic_imrashai@quicinc.com>



description: |

  Qualcomm graphics clock control module provides the clocks, resets and power
@@ -23,10 +24,12 @@ description: | 
    include/dt-bindings/clock/qcom,gpucc-sm8150.h

    include/dt-bindings/clock/qcom,gpucc-sm8250.h

    include/dt-bindings/clock/qcom,gpucc-sm8350.h

    include/dt-bindings/clock/qcom,qcs8300-gpucc.h



properties:

  compatible:

    enum:

      - qcom,qcs8300-gpucc

      - qcom,sdm845-gpucc

      - qcom,sa8775p-gpucc

      - qcom,sc7180-gpucc

Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Anusha Rao <quic_anusha@quicinc.com>



description: |

  Qualcomm networking sub system clock control module provides the clocks,

  resets on IPQ9574



  See also::

    include/dt-bindings/clock/qcom,ipq9574-nsscc.h

    include/dt-bindings/reset/qcom,ipq9574-nsscc.h



properties:

  compatible:

    const: qcom,ipq9574-nsscc



  clocks:

    items:

      - description: Board XO source

      - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source

      - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source

      - description: GCC GPLL0 OUT AUX clock source

      - description: Uniphy0 NSS Rx clock source

      - description: Uniphy0 NSS Tx clock source

      - description: Uniphy1 NSS Rx clock source

      - description: Uniphy1 NSS Tx clock source

      - description: Uniphy2 NSS Rx clock source

      - description: Uniphy2 NSS Tx clock source

      - description: GCC NSSCC clock source



  '#interconnect-cells':

    const: 1



  clock-names:

    items:

      - const: xo

      - const: nss_1200

      - const: ppe_353

      - const: gpll0_out

      - const: uniphy0_rx

      - const: uniphy0_tx

      - const: uniphy1_rx

      - const: uniphy1_tx

      - const: uniphy2_rx

      - const: uniphy2_tx

      - const: bus



required:

  - compatible

  - clocks

  - clock-names



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>

    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>

    clock-controller@39b00000 {

      compatible = "qcom,ipq9574-nsscc";

      reg = <0x39b00000 0x80000>;

      clocks = <&xo_board_clk>,

               <&cmn_pll NSS_1200MHZ_CLK>,

               <&cmn_pll PPE_353MHZ_CLK>,

               <&gcc GPLL0_OUT_AUX>,

               <&uniphy 0>,

               <&uniphy 1>,

               <&uniphy 2>,

               <&uniphy 3>,

               <&uniphy 4>,

               <&uniphy 5>,

               <&gcc GCC_NSSCC_CLK>;

      clock-names = "xo",

                    "nss_1200",

                    "ppe_353",

                    "gpll0_out",

                    "uniphy0_rx",

                    "uniphy0_tx",

                    "uniphy1_rx",

                    "uniphy1_tx",

                    "uniphy2_rx",

                    "uniphy2_tx",

                    "bus";

      #clock-cells = <1>;

      #reset-cells = <1>;

    };

...

Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml

+2 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ properties: 
          - qcom,rpmcc-msm8998

          - qcom,rpmcc-qcm2290

          - qcom,rpmcc-qcs404

          - qcom,rpmcc-sdm429

          - qcom,rpmcc-sdm660

          - qcom,rpmcc-sm6115

          - qcom,rpmcc-sm6125
@@ -123,6 +124,7 @@ allOf: 
              - qcom,rpmcc-msm8998

              - qcom,rpmcc-qcm2290

              - qcom,rpmcc-qcs404

              - qcom,rpmcc-sdm429

              - qcom,rpmcc-sdm660

              - qcom,rpmcc-sm6115

              - qcom,rpmcc-sm6125

Documentation/devicetree/bindings/clock/qcom,sa8775p-camcc.yaml

+5 −1
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@@ -8,16 +8,20 @@ title: Qualcomm Camera Clock & Reset Controller on SA8775P 


maintainers:

  - Taniya Das <quic_tdas@quicinc.com>

  - Imran Shaik <quic_imrashai@quicinc.com>



description: |

  Qualcomm camera clock control module provides the clocks, resets and power

  domains on SA8775p.



  See also: include/dt-bindings/clock/qcom,sa8775p-camcc.h

  See also:

    include/dt-bindings/clock/qcom,qcs8300-camcc.h

    include/dt-bindings/clock/qcom,sa8775p-camcc.h



properties:

  compatible:

    enum:

      - qcom,qcs8300-camcc

      - qcom,sa8775p-camcc



  clocks: