Commit 3066c521 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-samsung', 'clk-imx', 'clk-rockchip', 'clk-clkdev' and... 

Merge branches 'clk-samsung', 'clk-imx', 'clk-rockchip', 'clk-clkdev' and 'clk-rate-exclusive' into clk-next

 - Increase dev_id len for clkdev lookups

* clk-samsung: (25 commits)
  clk: samsung: Add CPU clock support for Exynos850
  clk: samsung: Pass mask to wait_until_mux_stable()
  clk: samsung: Keep register offsets in chip specific structure
  clk: samsung: Keep CPU clock chip specific data in a dedicated struct
  clk: samsung: Pass register layout type explicitly to CLK_CPU()
  clk: samsung: Pass actual CPU clock registers base to CPU_CLK()
  clk: samsung: Group CPU clock functions by chip
  clk: samsung: Use single CPU clock notifier callback for all chips
  clk: samsung: Reduce params count in exynos_register_cpu_clock()
  clk: samsung: Pull struct exynos_cpuclk into clk-cpu.c
  clk: samsung: Improve clk-cpu.c style
  dt-bindings: clock: exynos850: Add CMU_CPUCLK0 and CMU_CPUCL1
  clk: samsung: gs101: add support for cmu_peric1
  clk: samsung: gs101: drop extra empty line
  dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit
  clk: samsung: exynos850: Propagate SPI IPCLK rate change
  clk: samsung: gs101: gpio_peric0_pclk needs to be kept on
  clk: samsung: exynos850: Add PDMA clocks
  dt-bindings: clock: tesla,fsd: Fix spelling mistake
  clk: samsung: gs101: add support for cmu_peric0
  ...

* clk-imx:
  clk: imx: imx8mp: Fix SAI_MCLK_SEL definition
  clk: imx: scu: Use common error handling code in imx_clk_scu_alloc_dev()
  clk: imx: composite-8m: Delete two unnecessary initialisations in __imx8m_clk_hw_composite()
  clk: imx: composite-8m: Less function calls in __imx8m_clk_hw_composite() after error detection

* clk-rockchip:
  clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent
  clk: rockchip: rk3588: use linked clock ID for GATE_LINK
  clk: rockchip: rk3588: fix indent
  clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
  dt-bindings: clock: rk3588: add missing PCLK_VO1GRF
  dt-bindings: clock: rk3588: drop CLK_NR_CLKS
  clk: rockchip: rk3588: fix CLK_NR_CLKS usage
  clk: rockchip: rk3568: Add PLL rate for 128MHz

* clk-clkdev:
  clkdev: Update clkdev id usage to allow for longer names

* clk-rate-exclusive:
  clk: Add a devm variant of clk_rate_exclusive_get()
parents 68e4ebd5 d289ca74 79b92ba0 3e76237e 99f4570c b0cde62e

Documentation/devicetree/bindings/clock/google,gs101-clock.yaml

+28 −4
Original line number Diff line number Diff line
@@ -30,14 +30,16 @@ properties: 
      - google,gs101-cmu-top

      - google,gs101-cmu-apm

      - google,gs101-cmu-misc

      - google,gs101-cmu-peric0

      - google,gs101-cmu-peric1



  clocks:

    minItems: 1

    maxItems: 2

    maxItems: 3



  clock-names:

    minItems: 1

    maxItems: 2

    maxItems: 3



  "#clock-cells":

    const: 1
@@ -85,8 +87,30 @@ allOf: 


        clock-names:

          items:

            - const: dout_cmu_misc_bus

            - const: dout_cmu_misc_sss

            - const: bus

            - const: sss



  - if:

      properties:

        compatible:

          contains:

            enum:

              - google,gs101-cmu-peric0

              - google,gs101-cmu-peric1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (24.576 MHz)

            - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)

            - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: ip



additionalProperties: false

Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml

+42 −0
Original line number Diff line number Diff line
@@ -36,6 +36,8 @@ properties: 
      - samsung,exynos850-cmu-aud

      - samsung,exynos850-cmu-cmgp

      - samsung,exynos850-cmu-core

      - samsung,exynos850-cmu-cpucl0

      - samsung,exynos850-cmu-cpucl1

      - samsung,exynos850-cmu-dpu

      - samsung,exynos850-cmu-g3d

      - samsung,exynos850-cmu-hsi
@@ -152,6 +154,46 @@ allOf: 
            - const: dout_core_mmc_embd

            - const: dout_core_sss



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos850-cmu-cpucl0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CPUCL0 switch clock (from CMU_TOP)

            - description: CPUCL0 debug clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_cpucl0_switch

            - const: dout_cpucl0_dbg



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos850-cmu-cpucl1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CPUCL1 switch clock (from CMU_TOP)

            - description: CPUCL1 debug clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: dout_cpucl1_switch

            - const: dout_cpucl1_dbg



  - if:

      properties:

        compatible:

Documentation/devicetree/bindings/clock/tesla,fsd-clock.yaml

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ maintainers: 


description: |

  FSD clock controller consist of several clock management unit

  (CMU), which generates clocks for various inteernal SoC blocks.

  (CMU), which generates clocks for various internal SoC blocks.

  The root clock comes from external OSC clock (24 MHz).



  All available clocks are defined as preprocessor macros in

drivers/clk/clk.c

+19 −0
Original line number Diff line number Diff line
@@ -942,6 +942,25 @@ int clk_rate_exclusive_get(struct clk *clk) 
}

EXPORT_SYMBOL_GPL(clk_rate_exclusive_get);



static void devm_clk_rate_exclusive_put(void *data)

{

	struct clk *clk = data;



	clk_rate_exclusive_put(clk);

}



int devm_clk_rate_exclusive_get(struct device *dev, struct clk *clk)

{

	int ret;



	ret = clk_rate_exclusive_get(clk);

	if (ret)

		return ret;



	return devm_add_action_or_reset(dev, devm_clk_rate_exclusive_put, clk);

}

EXPORT_SYMBOL_GPL(devm_clk_rate_exclusive_get);



static void clk_core_unprepare(struct clk_core *core)

{

	lockdep_assert_held(&prepare_lock);

drivers/clk/clkdev.c

+1 −1
Original line number Diff line number Diff line
@@ -144,7 +144,7 @@ void clkdev_add_table(struct clk_lookup *cl, size_t num) 
	mutex_unlock(&clocks_mutex);

}



#define MAX_DEV_ID	20

#define MAX_DEV_ID	24

#define MAX_CON_ID	16



struct clk_lookup_alloc {