Unverified Commit 63bfd78a authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-amlogic', 'clk-allwinner', 'clk-rockchip' and 'clk-qcom' into clk-next 

* clk-amlogic:
  clk: meson: Do not enable by default during compile testing
  clk: meson-g12a: add missing fclk_div2 to spicc

* clk-allwinner:
  clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
  dt-bindings: allwinner: add H616 DE33 clock binding
  clk: sunxi-ng: h616: Add LVDS reset for LCD TCON
  dt-bindings: clock: sun50i-h616-ccu: Add LVDS reset
  clk: sunxi: Do not enable by default during compile testing
  clk: sunxi-ng: Do not enable by default during compile testing

* clk-rockchip:
  clk: rockchip: rk3528: add slab.h header include
  clk: rockchip: rk3576: add missing slab.h include
  clk: rockchip: rename gate-grf clk file
  clk: rockchip: rename branch_muxgrf to branch_grf_mux
  clk: rockchip: Pass NULL as reg pointer when registering GRF MMC clocks
  clk: rockchip: rk3036: mark ddrphy as critical
  clk: rockchip: rk3036: fix implementation of usb480m clock mux
  dt-bindings: clock: rk3036: add SCLK_USB480M clock-id
  clk: rockchip: rk3528: Add SD/SDIO tuning clocks in GRF region
  clk: rockchip: Support MMC clocks in GRF region
  dt-bindings: clock: Add GRF clock definition for RK3528
  clk: rockchip: add GATE_GRFs for SAI MCLKOUT to rk3576
  clk: rockchip: introduce GRF gates
  clk: rockchip: introduce auxiliary GRFs
  dt-bindings: clock: rk3576: add IOC gated clocks
  clk: rockchip: rk3568: Add PLL rate for 33.3MHz
  clk: rockchip: Drop empty init callback for rk3588 PLL type
  clk: rockchip: rk3588: Add PLL rate for 1500 MHz

* clk-qcom:
  clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocks
  clk: qcom: gcc: Set FORCE_MEM_CORE_ON for gcc_ufs_axi_clk for 8650/8750
  clk: qcom: rpmh: make clkaN optional
  clk: qcom: Add support for Camera Clock Controller on QCS8300
  clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHz
  dt-bindings: clock: add SM6350 QCOM video clock bindings
  clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCs
  clk: qcom: Fix missing error check for dev_pm_domain_attach()
parents 3e515fc8 b2177850 0409ac48 09febae2 b176dab2

Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ properties: 
      - const: allwinner,sun50i-a64-de2-clk

      - const: allwinner,sun50i-h5-de2-clk

      - const: allwinner,sun50i-h6-de3-clk

      - const: allwinner,sun50i-h616-de33-clk

      - items:

          - const: allwinner,sun8i-r40-de2-clk

          - const: allwinner,sun8i-h3-de2-clk

Documentation/devicetree/bindings/clock/qcom,videocc.yaml

+20 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ description: | 
  domains on Qualcomm SoCs.



  See also::

    include/dt-bindings/clock/qcom,sm6350-videocc.h

    include/dt-bindings/clock/qcom,videocc-sc7180.h

    include/dt-bindings/clock/qcom,videocc-sc7280.h

    include/dt-bindings/clock/qcom,videocc-sdm845.h
@@ -26,6 +27,7 @@ properties: 
      - qcom,sc7180-videocc

      - qcom,sc7280-videocc

      - qcom,sdm845-videocc

      - qcom,sm6350-videocc

      - qcom,sm8150-videocc

      - qcom,sm8250-videocc
@@ -87,6 +89,24 @@ allOf: 
            - const: bi_tcxo

            - const: bi_tcxo_ao



  - if:

      properties:

        compatible:

          enum:

            - qcom,sm6350-videocc

    then:

      properties:

        clocks:

          items:

            - description: Video AHB clock from GCC

            - description: Board XO source

            - description: Sleep Clock source

        clock-names:

          items:

            - const: iface

            - const: bi_tcxo

            - const: sleep_clk



  - if:

      properties:

        compatible:

drivers/clk/meson/Kconfig

+8 −8
Original line number Diff line number Diff line
@@ -55,7 +55,7 @@ config COMMON_CLK_MESON_CPU_DYNDIV 
config COMMON_CLK_MESON8B

	bool "Meson8 SoC Clock controller support"

	depends on ARM

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_CLKC_UTILS

	select COMMON_CLK_MESON_MPLL
@@ -70,7 +70,7 @@ config COMMON_CLK_MESON8B 
config COMMON_CLK_GXBB

	tristate "GXBB and GXL SoC clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_VID_PLL_DIV
@@ -86,7 +86,7 @@ config COMMON_CLK_GXBB 
config COMMON_CLK_AXG

	tristate "AXG SoC clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_MPLL
@@ -136,7 +136,7 @@ config COMMON_CLK_A1_PERIPHERALS 
config COMMON_CLK_C3_PLL

	tristate "Amlogic C3 PLL clock controller"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_PLL

	select COMMON_CLK_MESON_CLKC_UTILS
@@ -149,7 +149,7 @@ config COMMON_CLK_C3_PLL 
config COMMON_CLK_C3_PERIPHERALS

	tristate "Amlogic C3 peripherals clock controller"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_CLKC_UTILS
@@ -163,7 +163,7 @@ config COMMON_CLK_C3_PERIPHERALS 
config COMMON_CLK_G12A

	tristate "G12 and SM1 SoC clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

	select COMMON_CLK_MESON_MPLL
@@ -181,7 +181,7 @@ config COMMON_CLK_G12A 
config COMMON_CLK_S4_PLL

	tristate "S4 SoC PLL clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_CLKC_UTILS

	select COMMON_CLK_MESON_MPLL

	select COMMON_CLK_MESON_PLL
@@ -194,7 +194,7 @@ config COMMON_CLK_S4_PLL 
config COMMON_CLK_S4_PERIPHERALS

	tristate "S4 SoC peripherals clock controllers support"

	depends on ARM64

	default y

	default ARCH_MESON

	select COMMON_CLK_MESON_CLKC_UTILS

	select COMMON_CLK_MESON_REGMAP

	select COMMON_CLK_MESON_DUALDIV

drivers/clk/meson/g12a.c

+1 −0
Original line number Diff line number Diff line
@@ -4093,6 +4093,7 @@ static const struct clk_parent_data spicc_sclk_parent_data[] = { 
	{ .hw = &g12a_clk81.hw },

	{ .hw = &g12a_fclk_div4.hw },

	{ .hw = &g12a_fclk_div3.hw },

	{ .hw = &g12a_fclk_div2.hw },

	{ .hw = &g12a_fclk_div5.hw },

	{ .hw = &g12a_fclk_div7.hw },

};

drivers/clk/qcom/apcs-sdx55.c

+5 −1
Original line number Diff line number Diff line
@@ -111,7 +111,11 @@ static int qcom_apcs_sdx55_clk_probe(struct platform_device *pdev) 
	 * driver, there seems to be no better place to do this. So do it here!

	 */

	cpu_dev = get_cpu_device(0);

	dev_pm_domain_attach(cpu_dev, true);

	ret = dev_pm_domain_attach(cpu_dev, true);

	if (ret) {

		dev_err_probe(dev, ret, "can't get PM domain: %d\n", ret);

		goto err;

	}



	return 0;